公开(公告)号：US20240047002A1

公开(公告)日：2024-02-08

申请号：US18483448

申请日：2023-10-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Giacomo Pedretti ,  John Paul Strachan ,  Catherine Graves

IPC: G11C27/00 ,  G11C15/04

CPC classification number: G11C27/005 ,  G11C15/046

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

公开(公告)号：US11783878B2

公开(公告)日：2023-10-10

申请号：US17453585

申请日：2021-11-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Thomas Van Vaerenbergh ,  Can Li ,  Catherine Graves

IPC: G11C7/22 ,  G11C7/10 ,  G11C15/04 ,  G11C13/04 ,  G11C11/42

CPC classification number: G11C7/222 ,  G11C7/1012 ,  G11C7/1054 ,  G11C7/1081 ,  G11C11/42 ,  G11C13/04 ,  G11C15/04

Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.

公开(公告)号：US20230307048A1

公开(公告)日：2023-09-28

申请号：US18326813

申请日：2023-05-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

公开(公告)号：US11551771B2

公开(公告)日：2023-01-10

申请号：US17326223

申请日：2021-05-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Can Li ,  Catherine Graves

IPC: G11C15/04 ,  G11C27/00

Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

公开(公告)号：US20220375536A1

公开(公告)日：2022-11-24

申请号：US17326223

申请日：2021-05-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Can Li ,  Catherine Graves

IPC: G11C27/00 ,  G11C15/04

Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

公开(公告)号：US20220122646A1

公开(公告)日：2022-04-21

申请号：US17071924

申请日：2020-10-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  Can Li ,  Kivanc Ozonat ,  John Paul Strachan

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/06 ,  G06F9/38

Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.

公开(公告)号：US20210343341A1

公开(公告)日：2021-11-04

申请号：US16862997

申请日：2020-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Can Li

IPC: G11C15/04

Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.

公开(公告)号：US11024379B2

公开(公告)日：2021-06-01

申请号：US16667773

申请日：2019-10-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit Sharma ,  John Paul Strachan ,  Suhas Kumar ,  Catherine Graves ,  Martin Foltin ,  Craig Warner

IPC: G11C11/00 ,  G11C13/00

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

公开(公告)号：US10930348B1

公开(公告)日：2021-02-23

申请号：US16539868

申请日：2019-08-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/00 ,  G11C15/04 ,  G11C11/408 ,  G11C11/413 ,  G11C8/12

Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.

公开(公告)号：US20210021620A1

公开(公告)日：2021-01-21

申请号：US17042778

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  John Paul Strachan

IPC: H04L29/06

Abstract: A secondary ternary content-addressable memory (TCAM) is programmed with a new regular expression to be added to a regular expression pattern set. Incoming data strings are processed against a primary TCAM programmed with the regular expression pattern set and against the secondary TCAM in parallel.
While the incoming data strings are processed against the primary TCAM and against the secondary TCAM in parallel, the regular expression pattern set is updated to add the new regular expression.