公开(公告)号：US11912024B2

公开(公告)日：2024-02-27

申请号：US17951929

申请日：2022-09-23

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Michael W. Cumbie ,  James Michael Gardner ,  Scott A. Linn ,  George H. Corrigan, III

IPC: B41J2/045 ,  G01K13/02 ,  B41J2/14

CPC classification number: B41J2/04563 ,  B41J2/04546 ,  G01K13/026 ,  B41J2002/14491 ,  B41J2202/13

Abstract: A print component integrated circuitry package includes a number of temperature sensors where each of the plurality of the temperature sensors is disposed in a corresponding temperature region of an integrated circuitry. In an example, an analog sense bus conductively connects to all of the plurality of temperature sensors and an external sensor pad that is to connect to a corresponding print controller contact.

公开(公告)号：US11840075B2

公开(公告)日：2023-12-12

申请号：US17863934

申请日：2022-07-13

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： John Rossi ,  Erik D. Ness ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/36 ,  B41J2/045

CPC classification number: B41J2/0454 ,  B41J2/04541 ,  B41J2/04546 ,  B41J2/04563 ,  B41J2/04586

Abstract: An integrated circuit includes thermal tracking logic, control logic, and an output interface. The thermal tracking logic determines a temperature of a fluid ejection die. The control logic defines an emulated parameter of the fluid ejection die as a function of the temperature of the fluid ejection die. The output interface outputs the emulated parameter to a printer system based on the function and the temperature of the fluid ejection die.

公开(公告)号：US20230382105A1

公开(公告)日：2023-11-30

申请号：US18448794

申请日：2023-08-11

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10

CPC classification number: B41J2/04536 ,  B41J2/04586 ,  G06F3/1293 ,  B41J2/04541 ,  B41J2/04555 ,  B41J2/04563 ,  B41J2/0458 ,  G06F13/1668 ,  G11C7/1069 ,  G11C16/10

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US11780222B2

公开(公告)日：2023-10-10

申请号：US17961476

申请日：2022-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

CPC classification number: B41J2/04536 ,  B41J2/0458 ,  B41J2/04541 ,  B41J2/04555 ,  B41J2/04563 ,  B41J2/04586 ,  G06F3/1293 ,  G06F13/1668 ,  G11C7/1069 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/105

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20230302790A1

公开(公告)日：2023-09-28

申请号：US18202217

申请日：2023-05-25

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: G11C7/10 ,  B41J2/045 ,  B41J2/14

CPC classification number: B41J2/04551 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2/04581 ,  B41J2/14072 ,  B41J2/14201 ,  B41J2/1433 ,  G11C7/1072 ,  B41J2002/14491

Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays. A data block is associated with each of the plurality of fluidic actuator arrays. The die includes an interface comprising a data pad and a clock pad, wherein a data bit value present at the data pad is loaded into a first data block corresponding to a first fluidic actuator array on a rising clock edge and loaded into a second data block corresponding to a second fluidic actuator array on a falling clock edge.

公开(公告)号：US11676645B2

公开(公告)日：2023-06-13

申请号：US16956703

申请日：2019-02-06

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: G11C7/24 ,  B41J2/045 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/24 ,  B41J2/0458 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04551 ,  G11C7/10 ,  G11C13/004

Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.

公开(公告)号：US11548276B2

公开(公告)日：2023-01-10

申请号：US16959065

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Erik D. Ness

IPC: B41J29/38 ,  B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.

公开(公告)号：US11498328B2

公开(公告)日：2022-11-15

申请号：US16957518

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James M. Gardner

IPC: B41J2/045 ,  B41J29/393

Abstract: An integrated circuit to drive a plurality of actuators during a non-reset operating condition is disclosed. The integrated circuit includes a reset input to receive a reset signal activated for a duration. The reset signal generates a reset condition in the integrated circuit during which the non-reset operating condition is blocked. The integrated circuit also includes a monitor circuit operably coupled to the reset input to indicate if the duration of the reset signal meets or exceeds a selected duration.

公开(公告)号：US20220274399A1

公开(公告)日：2022-09-01

申请号：US17748913

申请日：2022-05-19

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: B41J2/045

Abstract: A fluid ejection die includes a plurality of first memory cells, a plurality of first storage elements, and control logic. Each first memory cell stores a customization bit. Each first storage element is coupled to a corresponding first memory cell. The control logic, in response to a reset signal, reads the customization bit stored in each first memory cell and latches each customization bit in a corresponding first storage element.

公开(公告)号：US11413864B2

公开(公告)日：2022-08-16

申请号：US16766523

申请日：2019-02-06

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael Gardner ,  Anthony M. Fuller ,  Michael W. Cumbie ,  Scott A. Linn

IPC: B41J2/14 ,  B41J2/045

Abstract: A die for a printhead is described herein. The die includes a number of fluid feed holes disposed in a line parallel to a longitudinal axis of the die, wherein the fluid feed holes are formed through a substrate of the die. A number of fluidic actuators are proximate to the fluid feed holes to eject fluid received from the plurality of fluid feed holes. The die includes logic circuitry to operate the fluidic actuators, wherein the logic circuitry is disposed on a first side of the plurality of fluid feed holes. Power circuitry to power the plurality of fluidic actuators is disposed on an opposite side of the fluid feed holes from the logic circuitry. Activation traces are disposed between each of the fluid feed holes to couple the logic circuitry to the power circuitry.