公开(公告)号：US10312943B2

公开(公告)日：2019-06-04

申请号：US15468619

申请日：2017-03-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

IPC: H03M13/00 ,  H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

公开(公告)号：US10157668B2

公开(公告)日：2018-12-18

申请号：US15566867

申请日：2015-05-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Luke Whitaker ,  Emmanuelle J. Merced Grafals ,  Martin Foltin

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.

公开(公告)号：US10056140B2

公开(公告)日：2018-08-21

申请号：US15112767

申请日：2014-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Yoocharn Jeon ,  Martin Foltin

IPC: G11C13/00 ,  G11C14/00

CPC classification number: G11C13/0035 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/00

Abstract: In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

公开(公告)号：US20170206956A1

公开(公告)日：2017-07-20

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

公开(公告)号：US20160343435A1

公开(公告)日：2016-11-24

申请号：US15112767

申请日：2014-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Yoocharn Jeon ,  Martin Foltin

IPC: G11C13/00

CPC classification number: G11C13/0035 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/00

Abstract: A memristor memory is disclosed. In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

Abstract translation: 忆阻记忆体被公开。 在一个示例中，控制忆阻存储器的方法包括以易失性模式操作忆阻器存储器，其中，忆阻单元的状态切换具有低的写入负载。 该方法还包括在非易失性模式下操作相同的忆阻器存储器，其中开关忆阻器单元的状态具有高写入负载。