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    Memory controller
    1.
    发明授权
    Memory controller 有权

    公开(公告)号：US10176043B2

    公开(公告)日：2019-01-08

    申请号：US15314902

    申请日：2014-07-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. Lesartre ,  Chris Michael Brueggen ,  Lidia Warnes

    IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  G06F11/20

    Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.

    LIST DECODE CIRCUITS
    2.
    发明申请
    LIST DECODE CIRCUITS 审中-公开

    公开(公告)号：US20180219560A1

    公开(公告)日：2018-08-02

    申请号：US15417431

    申请日：2017-01-27

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Chris Michael Brueggen ,  Ron M. Roth

    IPC: H03M13/15 ,  H03M13/00

    CPC classification number: H03M13/153 ,  H03M13/1515 ,  H03M13/1565 ,  H03M13/158 ,  H03M13/6502

    Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

    Detection of error patterns in memory dies
    4.
    发明授权
    Detection of error patterns in memory dies 有权

    公开(公告)号：US10275307B2

    公开(公告)日：2019-04-30

    申请号：US15454813

    申请日：2017-03-09

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen

    IPC: G06F11/10 ,  G11C29/52

    Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

    ERROR CORRECTION CODE IN MEMORY
    7.
    发明申请
    ERROR CORRECTION CODE IN MEMORY 审中-公开

    公开(公告)号：US20180276068A1

    公开(公告)日：2018-09-27

    申请号：US15468619

    申请日：2017-03-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

    CPC classification number: H03M13/2906 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

    LIST DECODE CIRCUITS
    8.
    发明申请
    LIST DECODE CIRCUITS 审中-公开

    公开(公告)号：US20180212625A1

    公开(公告)日：2018-07-26

    申请号：US15416395

    申请日：2017-01-26

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Chris Michael Brueggen

    IPC: H03M13/15 ,  G06F11/10 ,  H03M13/37 ,  H03M13/00

    CPC classification number: H03M13/153 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/3707 ,  H03M13/3723 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/6508 ,  H03M13/6561

    Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.

    List decode circuits
    9.
    发明授权
    List decode circuits 有权

    公开(公告)号：US10567003B2

    公开(公告)日：2020-02-18

    申请号：US15416395

    申请日：2017-01-26

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Chris Michael Brueggen

    IPC: H03M13/15 ,  H03M13/37 ,  H03M13/00

    Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.

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