公开(公告)号：US10156583B2

公开(公告)日：2018-12-18

申请号：US15051856

申请日：2016-02-24

Applicant: Intel Corporation

Inventor： Qing Ma ,  Valluri Rao ,  Feras Eid ,  Kevin Lin ,  Weng Hong Teh ,  Johanna M. Swan ,  Robert L. Sankman

IPC: H01F7/06 ,  G01P15/097 ,  G01P15/105 ,  G01P15/18

Abstract: A method of manufacturing an accelerometer, including placing a magnet on a substrate, laminating a dielectric layer over the magnet, forming a conductive layer over the dielectric layer, the conductive layer including a mass and a conductive path overlying the magnet, removing a portion of the dielectric layer proximate the mass and conductive path such that the mass is movable in response to acceleration of the accelerometer, and forming a dielectric layer over the mass to form a space between the mass and the dielectric layer formed over the mass sufficiently clear such that the mass remains movable.

公开(公告)号：US09947805B2

公开(公告)日：2018-04-17

申请号：US15151381

申请日：2016-05-10

Applicant: Intel Corporation

Inventor： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC: H01H51/22 ,  H01L29/84 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01H9/02

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

公开(公告)号：US09674945B2

公开(公告)日：2017-06-06

申请号：US13624288

申请日：2012-09-21

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

IPC: H01L23/34 ,  H05K1/02 ,  H01L25/00 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/0272 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0212 ,  H05K1/185 ,  H05K3/0097 ,  H05K2201/097 ,  H05K2203/1536 ,  H05K2203/308 ,  Y10T29/4913

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

公开(公告)号：US11798838B2

公开(公告)日：2023-10-24

申请号：US16358520

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Rishabh Mehandru ,  Hui Jae Yoo ,  Patrick Morrow ,  Kevin Lin

IPC: H01L21/768 ,  H01L21/683 ,  H01L21/762 ,  H01L23/31 ,  H01L29/417

CPC classification number: H01L21/7682 ,  H01L21/6836 ,  H01L21/76256 ,  H01L23/3171 ,  H01L29/41775 ,  H01L2221/68381

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11605592B2

公开(公告)日：2023-03-14

申请号：US16232524

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Kevin Lin ,  Kevin O'Brien ,  Hui Jae Yoo

IPC: H01L23/532 ,  H01L43/10 ,  H01L43/12 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

公开(公告)号：US11373900B2

公开(公告)日：2022-06-28

申请号：US17025087

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Robert L. Bristol ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US11367684B2

公开(公告)日：2022-06-21

申请号：US15985561

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Kevin Lin ,  Richard Vreeland

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321

Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.

公开(公告)号：US11335598B2

公开(公告)日：2022-05-17

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Sudipto Naskar ,  Manish Chandhok ,  Miriam Reshotko ,  Rami Hourani

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US11201114B2

公开(公告)日：2021-12-14

申请号：US16465119

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski ,  Richard F. Vreeland ,  Tristan A. Tronic

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/01 ,  H01L49/02

Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

公开(公告)号：US11164809B2

公开(公告)日：2021-11-02

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.