公开(公告)号：US11525970B2

公开(公告)日：2022-12-13

申请号：US17083173

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Gaurav Chawla

IPC: G06F13/14 ,  G02B6/42 ,  H01P5/00 ,  H01Q13/10 ,  H04B1/40 ,  H04B7/00 ,  H04M9/06 ,  G06F13/00

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US20220084949A1

公开(公告)日：2022-03-17

申请号：US17536804

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US11205630B2

公开(公告)日：2021-12-21

申请号：US16586158

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11189585B2

公开(公告)日：2021-11-30

申请号：US16703298

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

IPC: H01L23/52 ,  H01L23/00

Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

公开(公告)号：US20210343635A1

公开(公告)日：2021-11-04

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US11112841B2

公开(公告)日：2021-09-07

申请号：US16481396

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Divya Mani ,  William J. Lambert ,  Shawna Liff ,  Sergio A. Chan Arguedas ,  Robert L. Sankman

IPC: G06F1/20 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00 ,  H01Q23/00 ,  H04B1/40

Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.

公开(公告)号：US11094672B2

公开(公告)日：2021-08-17

申请号：US16586145

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US20210202347A1

公开(公告)日：2021-07-01

申请号：US16727703

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC: H01L23/373 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768

Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

公开(公告)号：US20210098411A1

公开(公告)日：2021-04-01

申请号：US16584522

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US10249515B2

公开(公告)日：2019-04-02

申请号：US15089136

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Eric Li ,  Shawna Liff

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/60

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.