公开(公告)号：US10169272B2

公开(公告)日：2019-01-01

申请号：US14827636

申请日：2015-08-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Jeorg Walter

IPC: G06F13/28 ,  G06F13/38 ,  G06F12/0862 ,  G06F12/084 ,  G06F3/06

Abstract: A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.

公开(公告)号：US20180365182A1

公开(公告)日：2018-12-20

申请号：US15808071

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F13/4282

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US10007625B2

公开(公告)日：2018-06-26

申请号：US14927055

申请日：2015-10-29

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/36 ,  G06F13/00 ,  G06F13/28 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/4022

Abstract: According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.

公开(公告)号：US09928000B2

公开(公告)日：2018-03-27

申请号：US15090765

申请日：2016-04-05

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/656 ,  G06F2212/68 ,  G06F2212/684

Abstract: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.

公开(公告)号：US09916268B2

公开(公告)日：2018-03-13

申请号：US14551798

申请日：2014-11-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F13/28 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0871

CPC classification number: G06F13/28 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

公开(公告)号：US20180018297A1

公开(公告)日：2018-01-18

申请号：US15209111

申请日：2016-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F12/0862 ,  G06F13/28 ,  G06F13/4022 ,  G06F2212/602

Abstract: Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.

公开(公告)号：US20170371813A1

公开(公告)日：2017-12-28

申请号：US15190262

申请日：2016-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott A. Brewer ,  David F. Craddock ,  Matthew J. Kalos ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/16 ,  G06F13/28 ,  G06F12/0815 ,  G06F12/0868

CPC classification number: G06F13/1689 ,  G06F12/0868 ,  G06F12/0886 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2213/28

Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

公开(公告)号：US09672099B2

公开(公告)日：2017-06-06

申请号：US15178788

申请日：2016-06-10

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Beth A. Glendening ,  Matthew J. Kalos ,  Matthias Klein ,  Eric N. Lais ,  Peter G. Sutton ,  Harry M. Yudenfriend

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/08 ,  G06F11/14 ,  G06F13/00

Abstract: Aspects include receiving, at an operating system (OS) executing on a server, a notification that an error was detected during execution of a synchronous I/O operation issued by the OS to a persistent storage control unit (SCU). The notification is received from firmware executing on the server and it includes a command response block that includes error condition information about the error. The method can also include selecting, by the OS, a recovery operation for the synchronous I/O operation. The selecting is based on the error condition information about the error in the command response block. The selected recovery option is performed by the OS.

公开(公告)号：US20170046276A1

公开(公告)日：2017-02-16

申请号：US14824107

申请日：2015-08-12

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

IPC: G06F12/12 ,  G06F12/10

CPC classification number: G06F12/122 ,  G06F9/5077 ,  G06F9/52 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/123 ,  G06F12/1425 ,  G06F12/1466 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/621 ,  G06F2212/657

Abstract: A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system. The memory unit includes a page table and an operating system, where each data block of the data blocks is accessed via a virtual address. The method further includes: adding an entry in the page table for each data block of a first set of the data blocks, the page table represents the virtual address; checking that a first entry of the added entries represents a first virtual address, in response to receiving a request of a first data block via the first virtual address by a memory management unit of the computer system; and obtaining a first physical address of the first data block from the hardware components, and the added entry is provided without indication of the first physical address.

Abstract translation: 一种用于访问存储在计算机系统中的数据块的方法。 该方法可以包括用于控制对计算机系统的存储器单元的访问的硬件组件。 存储单元包括页表和操作系统，其中通过虚拟地址访问数据块的每个数据块。 该方法还包括：在第一组数据块的每个数据块的页表中添加条目，页表表示虚拟地址; 响应于所述计算机系统的存储器管理单元经由所述第一虚拟地址接收到第一数据块的请求，检查所添加的条目的第一条目是否表示第一虚拟地址; 以及从所述硬件组件获得所述第一数据块的第一物理地址，并且提供所述添加的条目而不指示所述第一物理地址。

公开(公告)号：US09529618B2

公开(公告)日：2016-12-27

申请号：US14306816

申请日：2014-06-17

Applicant: International Business Machines Corporation

Inventor： Christian Borntraeger ,  Heiko Carstens ,  Dominik Dingel ,  Matthias Klein ,  Einar Lueck

IPC: G06F9/455 ,  G06F12/10 ,  H04L29/08 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/45533 ,  G06F9/4856 ,  G06F9/5077 ,  G06F12/1009 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45595 ,  H04L67/1008

Abstract: A process can be scheduled between first and second hosts that using a virtual file system that is shared between the hosts can be used. The process, running on a first hypervisor of the first host, can be scheduled to run on a second hypervisor of the second host. A file can be created that includes the data content of the process address space for the file. The file can be mapped address space of the virtual file system. Data from the physical memory of the first host can be transferred to physical memory of the second host using page fault routines.