公开(公告)号：US20190341447A1

公开(公告)日：2019-11-07

申请号：US16404284

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.

公开(公告)号：US20190097042A1

公开(公告)日：2019-03-28

申请号：US16144880

申请日：2018-09-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Romain Esteve ,  Roland Rupp

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.

公开(公告)号：US10049879B2

公开(公告)日：2018-08-14

申请号：US15582940

申请日：2017-05-01

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L29/15 ,  H01L21/04 ,  H01L29/16 ,  H01L21/324 ,  H01L29/45 ,  H01L21/02

Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

公开(公告)号：US10038087B2

公开(公告)日：2018-07-31

申请号：US15858730

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/861

Abstract: According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in the semiconductor body. Each device cell includes: a body region arranged between a source region and the drift region; a diode region and a pn junction between the diode region and the drift region; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; and a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric. The diode regions together with the drift region act as a JFET, which has a channel region in the drift region between the diode regions. The drift region has a locally increased doping concentration in the channel region of the JFET.

公开(公告)号：US09923053B2

公开(公告)日：2018-03-20

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L21/04 ,  H01L29/66

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

公开(公告)号：US20180053841A1

公开(公告)日：2018-02-22

申请号：US15798439

申请日：2017-10-31

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/04 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/36 ,  H01L21/265 ,  H01L29/872 ,  H01L29/861

CPC classification number: H01L29/7806 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes a body region arranged between source and drift regions in a semiconductor body. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench, and a pn junction is between the diode region and the drift region below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A further trench spaced apart from the gate trench extends from the first surface of the semiconductor body, through the source and diode regions and into the drift region. A source electrode arranged in the further trench adjoins the drift region in the further trench to form a Schottky contact with the drift region.

公开(公告)号：US20170345905A1

公开(公告)日：2017-11-30

申请号：US15162716

申请日：2016-05-24

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/20 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/4236 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7827

Abstract: A semiconductor device includes trench gate structures extending from a first surface into a semiconductor body from a wide-bandgap semiconductor material. The trench gate structures separate mesa portions of the semiconductor body from each other. In the mesa portions, body regions form first pn junctions with a drain structure and directly adjoin first mesa sidewalls. Source regions in the mesa portions form second pn junctions with the body regions, wherein the body regions separate the source regions from the drain structure. The source regions directly adjoin the first mesa sidewalls and second mesa sidewalls opposite to the first mesa sidewalls.

公开(公告)号：US09818818B2

公开(公告)日：2017-11-14

申请号：US15057669

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/04 ,  H01L29/423 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/045 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/02667 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body with a first main crystal direction parallel to a horizontal plane. Longitudinal axes of trench gate structures are tilted to the first main crystal direction by a tilt angle of at least 2 degree and at most 30 degree in the horizontal plane. Mesa portions are between neighboring trench gate structures. First sidewall sections of first mesa sidewalls are main crystal planes parallel to the first main crystal direction. Second sidewall sections tilted to the first sidewall sections connect the first sidewall sections.

公开(公告)号：US09666482B1

公开(公告)日：2017-05-30

申请号：US15265081

申请日：2016-09-14

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L29/15 ,  H01L21/768 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L21/0485 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/7802

Abstract: A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.

公开(公告)号：US20170117352A1

公开(公告)日：2017-04-27

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.