公开(公告)号：US20180095925A1

公开(公告)日：2018-04-05

申请号：US15283028

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Zuoguo Wu ,  Mahesh Wagh

IPC: G06F13/42 ,  G06F1/26

CPC classification number: G06F13/4265 ,  G06F1/3253 ,  Y02D10/14 ,  Y02D10/151

Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.

公开(公告)号：US09830292B2

公开(公告)日：2017-11-28

申请号：US14836234

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/40 ,  H04L12/24 ,  H04L12/917 ,  G06N99/00 ,  H04L12/911

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

公开(公告)号：US09710406B2

公开(公告)日：2017-07-18

申请号：US14570304

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  David J. Harriman ,  Mahesh Wagh ,  Abdul Hawk Ismail

IPC: G06F13/38 ,  G06F13/10 ,  G06F13/42 ,  G06F1/26 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F1/266 ,  G06F1/3203 ,  G06F13/287 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

公开(公告)号：US20170177528A1

公开(公告)日：2017-06-22

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4282

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US09558145B2

公开(公告)日：2017-01-31

申请号：US14991293

申请日：2016-01-08

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC: H04B17/00 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38 ,  G06F1/14

CPC classification number: G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US20160259400A1

公开(公告)日：2016-09-08

申请号：US15158271

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F1/32 ,  G06F13/42 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述用于将端口条目同步到最低功率状态的系统，装置和方法。 在进入最低功率状态之前，端口的所有逻辑被置于中间状态。

公开(公告)号：US09390046B2

公开(公告)日：2016-07-12

申请号：US14132610

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

公开(公告)号：US09262360B2

公开(公告)日：2016-02-16

申请号：US14132734

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  H04L12/24 ,  H04L12/917 ,  H04L12/911

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

公开(公告)号：US09262347B2

公开(公告)日：2016-02-16

申请号：US14126926

申请日：2013-10-30

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC: H04B17/00 ,  G06F13/00

CPC classification number: G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US09223735B2

公开(公告)日：2015-12-29

申请号：US14557699

申请日：2014-12-02

Applicant: INTEL CORPORATION

Inventor： David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/20 ,  G06F1/32 ,  G06N99/00

CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F13/20 ,  G06F13/4295 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。