-
公开(公告)号：US20170141914A1
公开(公告)日：2017-05-18
申请号：US14939141
申请日：2015-11-12
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vikram B. Suresh , Sanu K. Mathew
CPC classification number: H04L9/0618 , G06F9/30007 , G06F9/3877 , G06F21/602 , G06F21/72 , H04L9/0625 , H04L9/0643 , H04L2209/12 , H04L2209/125 , H04L2209/34
Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic includes a message scheduling module selectively operating in one of a SHA mode or an SM3 mode to generate a sequence of message words based on an incoming message. The processing logic also includes a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words.
-
52.发明授权公开(公告)号：US09515835B2
公开(公告)日：2016-12-06
申请号：US14667665
申请日：2015-03-24
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , Sudhir K. Satpathy
CPC classification number: H04L9/3278 , G06Q10/08 , G09C1/00 , H03K19/17768 , H04L2209/04 , H04L2209/12
Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
Abstract translation: 实施例包括用于物理不可克隆功能（PUF）电路的装置，方法和系统。 PUF电路可以包括PUF单元的阵列以产生加密代码的相应PUF位。 单个PUF单元可以包括交叉耦合在比特节点和比特列节点之间的第一和第二反相器。 单个PUF单元还可以包括耦合到比特节点并被配置为经由第一时钟路径接收时钟信号的第一预充电晶体管，以及耦合到比特列节点并被配置为接收时钟的第二预充电晶体管 经由第二时钟路径发送信号。 公开了PUF细胞的特征和技术以改善PUF细胞的稳定性和/或偏向强度，以产生PUF细胞阵列的暗位掩模，并提高对探测攻击的抵抗力。 可以描述和要求保护其他实施例。
-
公开(公告)号：US09513919B2
公开(公告)日：2016-12-06
申请号：US14698486
申请日：2015-04-28
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vinodh Gopal , James D. Guilford
CPC classification number: G06F9/30185 , G06F9/30021 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30156 , G06F9/3016 , H03M7/4037 , H03M7/6005 , H03M7/6023
Abstract: An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.
Abstract translation: 一种用于执行诸如霍夫曼码之类的前缀码的并行解码的装置和方法。 例如，装置的一个实施例包括：第一解压缩模块，用于执行包括第一多个符号的前缀码有效载荷的第一部分的非推测解压缩; 以及第二解压缩模块，用于执行与由第一压缩模块执行的非推测性解压缩同时地包括第二多个符号的前缀码有效载荷的第二部分的推测性解压缩。
-
公开(公告)号：US09503747B2
公开(公告)日：2016-11-22
申请号：US14607113
申请日：2015-01-28
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
CPC classification number: G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。 压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。 描述和要求保护其他实施例。
-
55.发明申请公开(公告)号：US20160285639A1
公开(公告)日：2016-09-29
申请号：US14667665
申请日：2015-03-24
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , Sudhir K. Satpathy
IPC: H04L9/32
CPC classification number: H04L9/3278 , G06Q10/08 , G09C1/00 , H03K19/17768 , H04L2209/04 , H04L2209/12
Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
Abstract translation: 实施例包括用于物理不可克隆功能（PUF）电路的装置，方法和系统。 PUF电路可以包括PUF单元的阵列以产生加密代码的相应PUF位。 单个PUF单元可以包括交叉耦合在比特节点和比特列节点之间的第一和第二反相器。 单个PUF单元还可以包括耦合到比特节点并被配置为经由第一时钟路径接收时钟信号的第一预充电晶体管，以及耦合到比特列节点并被配置为接收时钟的第二预充电晶体管 经由第二时钟路径发送信号。 公开了PUF细胞的特征和技术以改善PUF细胞的稳定性和/或偏向强度，以产生PUF细胞阵列的暗位掩模，并提高对探测攻击的抵抗力。 可以描述和要求保护其他实施例。
-
Patent Agency Ranking
公开(公告)号：US11483167B2
公开(公告)日：2022-10-25
申请号：US16447887
申请日：2019-06-20
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Manoj Sachdev , Sanu K. Mathew , Sudhir K. Satpathy
Abstract: Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (VT) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.
-
公开(公告)号：US20220224353A1
公开(公告)日：2022-07-14
申请号：US17586598
申请日：2022-01-27
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
-
公开(公告)号：US10985903B2
公开(公告)日：2021-04-20
申请号：US16158659
申请日：2018-10-12
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Sanu K. Mathew , Sudhir K. Satpathy , Vikram B. Suresh
Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.
-
公开(公告)号：US10320414B2
公开(公告)日：2019-06-11
申请号：US15875836
申请日：2018-01-19
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: This application sets forth methods and apparatus to parallelize data decompression. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
-
公开(公告)号：US10313108B2
公开(公告)日：2019-06-04
申请号：US15196686
申请日：2016-06-29
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sudhir K. Satpathy , Sanu K. Mathew
IPC: H04L9/06
Abstract: A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor.
-
-
-
-
-
-
-
-
-
Search Results
75
records
(took 0.019 seconds)
