公开(公告)号：US20180095161A1

公开(公告)日：2018-04-05

申请号：US15221347

申请日：2016-07-27

Applicant: RAYTHEON COMPANY

Inventor： Theodore M. Kellum ,  Walter B. Schulte, JR. ,  Harry B. Marr

IPC: G01S7/02 ,  H04W16/14 ,  H04B7/08 ,  H01Q3/26

CPC classification number: G01S7/023 ,  G01S7/021 ,  G01S7/282 ,  G01S13/10 ,  G01S13/86 ,  H01Q3/2658 ,  H01Q3/267 ,  H04B7/086 ,  H04W16/14

Abstract: A method for concurrent transmission of different signal types by a radar system includes: receiving a waveform request for transmitting a first signal type and a second signal type; determining whether the first signal or the second signal is optimized; when the first signal is optimized: transmitting the first and the second signal simultaneously in separate bands; and when the second signal is optimized: determining a time gap between transmission of the second signal, and adjusting pulse repetition interval (PRI) or pulse width of the first signal to fit in the time gap, transmitting the second signal, and transmitting the first signal in the time gap between the transmission of the second signal.

公开(公告)号：US09923549B2

公开(公告)日：2018-03-20

申请号：US14849524

申请日：2015-09-09

Applicant: Raytheon Company

Inventor： Denpol Kultran ,  Richard T. Hennegan ,  Harry B. Marr

IPC: H03H15/00 ,  H03H19/00

CPC classification number: H03H15/00 ,  H03H19/00

Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

公开(公告)号：US09753766B2

公开(公告)日：2017-09-05

申请号：US14553139

申请日：2014-11-25

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Craig A. Snow ,  Leo Linsky ,  Kellie Canida

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4818 ,  G06F9/5022 ,  G06F9/5027 ,  G06F2209/5021

Abstract: A system and method for allocating resources receive one or more resource requests describing tasks, each of the one or more resource requests having a request priority, a requested configuration type, and a requestor identifier. In a winner-take-all circuit, all of the existing resource priorities within each configuration of the requested configuration type are compared to determine a highest-priority task occupying each assignment. In a loser-take-all circuit, one or more current highest resource priorities of each configuration within the requested configuration type, which are output from the winner-take-all circuit associated with the requested resource assignment, each of the one or more current resources having a current priority, are compared. One of the one or more current resource configurations within the requested configuration type having the lowest current priority is identified as the lowest-priority current resource configuration. The requested configuration type is allocated to the selected resource request if the request priority is higher than the lowest current priority configuration output from the loser-take-all circuit. The method further comprises continuing to allocate the requested configuration type to the lowest-priority current resource tasks currently occupying the lowest current priority configuration within the requested configuration if the lowest current priority configuration within the requested configuration is higher than or equal to the request priority.

公开(公告)号：US09485125B2

公开(公告)日：2016-11-01

申请号：US14305685

申请日：2014-06-16

Applicant: Raytheon Company

Inventor： Daniel Thompson ,  Harry B. Marr ,  Nnaemeka Okafor ,  Chris McLean ,  Aaron Romulo ,  Edwin Molina

IPC: H04J3/04 ,  H04L27/00 ,  H04B1/00 ,  H04L27/26

CPC classification number: H04L27/00 ,  H04B1/001 ,  H04B1/0035 ,  H04J3/02 ,  H04J3/1694 ,  H04L27/2652 ,  H04L27/2657

Abstract: Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object.

Abstract translation: 实施例涉及一种被配置为通过以下方式提供完全可配置的频谱整形的信道器架构：通过以下方式提供架构的多个参数，接收输入信号，根据该结构处理输入信号，以获得 输出信号，分析输出信号以检测对象，以及修改多个参数以解决与对象相关联的至少一个动态条件。

公开(公告)号：US09385831B2

公开(公告)日：2016-07-05

申请号：US13910731

申请日：2013-06-05

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Daniel Thompson ,  Julia Karl

IPC: H04K3/00 ,  G06F1/02

CPC classification number: H04K3/42 ,  G06F1/022 ,  H04K3/00 ,  H04K3/44

Abstract: Embodiments of a system and method for providing efficient wideband inverse channelization for direct digital synthesizer based jamming techniques are generally described herein. In some embodiments, metadata associated with a technique for generating a waveform, such as frequency, phase and amplitude parameters, is received. Data select signals and data input are generated based on the received metadata. In-phase and quadrature signals are produced at an output of a first de-multiplexer and a second de-multiplexer, respectively, based on the data select signals and the data input. Frequency modulated signals generated by direct digital synthesizers may be combined in a channel using a separate, distinct channel combiner.

Abstract translation: 本文通常描述用于为基于直接数字合成器的干扰技术提供有效的宽带反向信道化的系统和方法的实施例。 在一些实施例中，接收与用于生成波形的技术（例如频率，相位和幅度参数）相关联的元数据。 基于接收的元数据生成数据选择信号和数据输入。 基于数据选择信号和数据输入，分别在第一解复用器和第二解复用器的输出端产生同相和正交信号。 由直接数字合成器产生的频率调制信号可以使用单独的，不同的信道组合器在信道中组合。

公开(公告)号：US08791849B1

公开(公告)日：2014-07-29

申请号：US13827892

申请日：2013-03-14

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Ralston S. Robertson ,  Ronak D. Shah

IPC: H03M1/66

CPC classification number: H03M1/66

Abstract: A system for converting a digital signal to an analog signal, the digital signal having a center frequency, includes: a multi-Nyquist DAC; a clock; and a controller configured to: control the clock to generate a clock signal such that the center frequency of the digital signal is an integer multiple of half the frequency of the clock signal, the clock being configured to supply the clock signal to the multi-Nyquist DAC and to the controller; and supply the digital signal to the multi-Nyquist DAC to generate an output signal.

Abstract translation: 一种用于将数字信号转换为模拟信号的系统，具有中心频率的数字信号包括：多奈奎斯特DAC; 一个钟; 以及控制器，其被配置为：控制所述时钟以产生时钟信号，使得所述数字信号的中心频率是所述时钟信号的频率的一半的整数倍，所述时钟被配置为将所述时钟信号提供给所述多奈奎斯特 DAC和控制器; 并将数字信号提供给多奈奎斯特DAC以产生输出信号。