公开(公告)号：US11024585B2

公开(公告)日：2021-06-01

申请号：US16005348

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US20200335478A1

公开(公告)日：2020-10-22

申请号：US16918281

申请日：2020-07-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/786 ,  H01L21/784 ,  H01L21/782 ,  H01L21/82 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

公开(公告)号：US20200325014A1

公开(公告)日：2020-10-15

申请号：US16912902

申请日：2020-06-26

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: B81B7/00

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

公开(公告)号：US20200219832A1

公开(公告)日：2020-07-09

申请号：US16826216

申请日：2020-03-21

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi Chelvam Marimuthu ,  Andy Chang Bum Yong ,  Aung Kyaw Oo ,  Yaojian Lin

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

公开(公告)号：US10662056B2

公开(公告)日：2020-05-26

申请号：US16169817

申请日：2018-10-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

公开(公告)号：US10446459B2

公开(公告)日：2019-10-15

申请号：US15618343

申请日：2017-06-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Thomas J. Strothmann ,  Seung Wook Yoon ,  Yaojian Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.

公开(公告)号：US10297519B2

公开(公告)日：2019-05-21

申请号：US15676881

申请日：2017-08-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin

IPC: H01L23/31 ,  H01L25/00 ,  H01L23/552 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10 ,  H01L23/36 ,  H01L23/13 ,  H01L23/373 ,  H01L23/498 ,  H01L21/66 ,  H01L25/065 ,  H05K1/18 ,  H05K3/28

Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

公开(公告)号：US10297518B2

公开(公告)日：2019-05-21

申请号：US15167662

申请日：2016-05-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

公开(公告)号：US10242948B2

公开(公告)日：2019-03-26

申请号：US15380788

申请日：2016-12-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Jun Mo Koo ,  Pandi C. Marimuthu ,  Yaojian Lin ,  See Chian Lim

IPC: H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

公开(公告)号：US10217702B2

公开(公告)日：2019-02-26

申请号：US15167830

申请日：2016-05-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L21/78 ,  H01L23/538

Abstract: A semiconductor device includes a BGA package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.