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    Antenna in Embedded Wafer-Level Ball-Grid Array Package
    1.
    发明申请
    Antenna in Embedded Wafer-Level Ball-Grid Array Package 审中-公开

    公开(公告)号：US20200219832A1

    公开(公告)日：2020-07-09

    申请号：US16826216

    申请日：2020-03-21

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Pandi Chelvam Marimuthu ,  Andy Chang Bum Yong ,  Aung Kyaw Oo ,  Yaojian Lin

    IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683

    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

    Method of packaging thin die and semiconductor device including thin die
    2.
    发明授权
    Method of packaging thin die and semiconductor device including thin die 有权

    公开(公告)号：US10510632B2

    公开(公告)日：2019-12-17

    申请号：US15919401

    申请日：2018-03-13

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

    IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56

    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.

    Method of Packaging Thin Die and Semiconductor Device Including Thin Die
    3.
    发明申请
    Method of Packaging Thin Die and Semiconductor Device Including Thin Die 审中-公开

    公开(公告)号：US20190287873A1

    公开(公告)日：2019-09-19

    申请号：US15919401

    申请日：2018-03-13

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

    IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768

    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.

    Antenna in Embedded Wafer-Level Ball-Grid Array Package
    7.
    发明申请
    Antenna in Embedded Wafer-Level Ball-Grid Array Package 审中-公开

    公开(公告)号：US20190088603A1

    公开(公告)日：2019-03-21

    申请号：US16184134

    申请日：2018-11-08

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Pandi Chelvam Marimuthu ,  Andy Chang Bum Yong ,  Aung Kyaw Oo ,  Yaojian Lin

    IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/522 ,  H01L23/552 ,  H01L23/538 ,  H01L21/48 ,  H01L23/528

    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

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