公开(公告)号：US20250167153A1

公开(公告)日：2025-05-22

申请号：US18932984

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Okseon Yoon ,  Jinyoung Kim ,  Jiyoung Yoon ,  Kiseok Kim ,  Jihye Shim

IPC: H01L23/00 ,  G03F7/028

Abstract: A method of forming a redistribution pad, the method including forming a hole exposing a redistribution pattern in a redistribution insulating layer and forming a photoresist composition on a surface of the redistribution insulating layer and filling the hole. The photoresist composition including at least one first photoinitiator and at least one first crosslinking agent that cause a crosslinking reaction by a first light and at least one second photoinitiator and at least one second crosslinking agent that cause a crosslinking reaction by a second light having a different wavelength from the first light. The method further includes irradiating the first light to the photoresist composition, forming a photoresist pattern having a pattern hole using the photoresist composition to which the first light is irradiated, irradiating the second light to the photoresist pattern, and forming the redistribution pad using the photoresist pattern to which the second light is irradiated.

公开(公告)号：US20250125205A1

公开(公告)日：2025-04-17

申请号：US18674416

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Kiseok Kim ,  Jinyoung Kim ,  Jihye Shim

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including first pads, a second semiconductor chip including second pads in contact with the first pads, and through-electrodes electrically connected to the second pads and extending to a rear surface opposite to the front surface, a dielectric layer covering at least portions of the respective first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface, and bump structures on a portion of the outer surface of the dielectric layer and electrically connected to the through-electrodes. The dielectric layer includes inorganic particles, and polymer chains bonded to at least one sides of the respective inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles.

公开(公告)号：US20250053302A1

公开(公告)日：2025-02-13

申请号：US18671484

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Jisang Lee ,  Joonsuc Jang

IPC: G06F3/06

Abstract: An example memory device includes a memory cell array, a page buffer including buffer units corresponding to a plurality of memory cells of a page, a control logic configured to control a first read operation such that first hard decision data based on a normal read level and first soft decision data based on an offset level with respect to a first page are stored in the page buffer. The control logic is configured to perform a control operation of outputting the first hard decision data to a memory controller after a second read operation with respect to a second page has started in response to a first command that requests read of the second page from the memory controller and outputting the first soft decision data to the memory controller while the second read operation is being performed in response to a second command from the memory controller.

公开(公告)号：US12094552B2

公开(公告)日：2024-09-17

申请号：US18374026

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C7/10 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11972791B2

公开(公告)日：2024-04-30

申请号：US17689480

申请日：2022-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojung Jang ,  Jinyoung Kim ,  Sehwan Park ,  Jisang Lee

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4099

CPC classification number: G11C11/4096 ,  G11C7/1039 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4099

Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells having a plurality of states including a first state and a second state, a first read operation for the first state is performed, and a second read operation for the second state is performed. To perform the first read operation, cell counts for a valley of the first state are obtained by performing a valley cell count operation for the first state, a first read voltage level for the first state is determined based on the cell counts and at least one first reference parameter for the first state, and a first sensing operation for the first state is performed by using the first read voltage level. To perform the second read operation, a second read voltage level for the second state is determined based on the cell counts and at least one second reference parameter for the second state, and a second sensing operation for the second state is performed by using the second read voltage level.

公开(公告)号：US11749356B2

公开(公告)日：2023-09-05

申请号：US17450871

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C5/14

CPC classification number: G11C16/30 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  G11C5/147 ,  G11C5/148 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory system includes a non-volatile memory device including a machine learning (ML) module and a peripheral power management integrated circuit (IC), and a memory controller configured to command the non-volatile memory device to enter an idle mode by providing an external power command to the non-volatile memory device. The machine learning (ML) module configures a neural network and trains the neural network via machine learning, and the peripheral power management IC is configured to generate an internal power command that is different from the external power command based on the external power command and monitoring information corresponding to the ML module.

公开(公告)号：US11688461B2

公开(公告)日：2023-06-27

申请号：US17705613

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Makoto Hirano ,  Jinyoung Kim

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/004 ,  G11C13/0026 ,  G11C2213/71 ,  G11C2213/79

Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.

公开(公告)号：US11670661B2

公开(公告)日：2023-06-06

申请号：US16934278

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Euiyeol Kim ,  Hyounmin Baek ,  Jeong-Ho Lee ,  Youngwoo Chung ,  Heegeun Jeong

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14689

Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

公开(公告)号：US20230154885A1

公开(公告)日：2023-05-18

申请号：US18049428

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Jiyeong Kim ,  Okseon Yoon

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L24/73 ,  H01L21/563 ,  H01L23/295 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/2929 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05617 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/16146 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

公开(公告)号：US11579972B2

公开(公告)日：2023-02-14

申请号：US17399528

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongmin Shin ,  Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo

IPC: G06F11/10 ,  H03M13/45

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.