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公开(公告)号：US10068608B1
公开(公告)日：2018-09-04
申请号：US15723969
申请日：2017-10-03
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.
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公开(公告)号：US20240144959A1
公开(公告)日：2024-05-02
申请号：US18405516
申请日：2024-01-05
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/09 , G06F13/385 , H03M1/12 , G11B2005/0013
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end circuit, and performing analog offset compensation to constrain the extrema of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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53.发明授权公开(公告)号：US11949435B2
公开(公告)日：2024-04-02
申请号：US17475552
申请日：2021-09-15
Applicant: Seagate Technology LLC
Inventor： William M. Radich , Raman Venkataramani , Jason Bellorado , Marcus Marrow , Zheng Wang
CPC classification number: H03M13/4138 , G06N7/01 , H03M13/01 , H03M13/3961 , H03M13/45
Abstract: A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K>1. Markov transition probabilities are determined that depend on a discrete phase ϕ=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.
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公开(公告)号：US11495260B1
公开(公告)日：2022-11-08
申请号：US17353245
申请日：2021-06-21
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Rishi Ahuja , William M. Radich , Ara Patapoutian
Abstract: A plurality of configuration sets are used with a detector coupled to a decoder. A processor is coupled to the memory registers and the detector and operable to load a first one of the configuration sets into the detector. The detector to attempts detection of the bits in the digital stream for a first iteration between the detector and the decoder using the first configuration set. After the first iteration, a second one of the configuration sets is loaded into the detector. The second configuration set is different than the first configuration set. The detector to attempts detection of the bits in the digital stream for a second iteration between the detector and the decoder using the second configuration set.
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公开(公告)号：US20220286147A1
公开(公告)日：2022-09-08
申请号：US17825905
申请日：2022-05-26
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Marcus Marrow , Jason Bellorado
Abstract: A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N−L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.
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Patent Agency Ranking
公开(公告)号：US11362681B2
公开(公告)日：2022-06-14
申请号：US16999250
申请日：2020-08-21
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Marcus Marrow , Jason Bellorado
Abstract: In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.
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公开(公告)号：US11361788B2
公开(公告)日：2022-06-14
申请号：US16672718
申请日：2019-11-04
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , G06F13/10 , G06F13/42 , G06F1/08 , G06F1/12 , H04L25/03 , H03L7/093 , H03L7/095 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00 , H04L7/033 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03G3/20 , H03M1/12 , H03M13/29 , H04B1/7105 , H03K5/00
Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.
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公开(公告)号：US11341998B1
公开(公告)日：2022-05-24
申请号：US17016484
申请日：2020-09-10
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.
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公开(公告)号：US20220060199A1
公开(公告)日：2022-02-24
申请号：US16999250
申请日：2020-08-21
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Marcus Marrow , Jason Bellorado
Abstract: In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.
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公开(公告)号：US20200065262A1
公开(公告)日：2020-02-27
申请号：US16672718
申请日：2019-11-04
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.
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