公开(公告)号：US12099379B2

公开(公告)日：2024-09-24

申请号：US18079324

申请日：2022-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F1/00 ,  G06F1/14 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3287

CPC classification number: G06F1/14 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3287

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

公开(公告)号：US12072776B2

公开(公告)日：2024-08-27

申请号：US18166787

申请日：2023-02-09

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F13/20

CPC classification number: G06F11/1616 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/1441 ,  G06F13/20 ,  G06F2201/805

Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

公开(公告)号：US20240187015A1

公开(公告)日：2024-06-06

申请号：US18437510

申请日：2024-02-09

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G ,  Srinivasa Chakravarthy

IPC: H03M1/12 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/00 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/00 ,  G06F13/28 ,  G06F2213/28

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

公开(公告)号：US11967397B2

公开(公告)日：2024-04-23

申请号：US17710879

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22

CPC classification number: G11C7/109 ,  G11C5/14 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/222

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

公开(公告)号：US20240063816A1

公开(公告)日：2024-02-22

申请号：US18500344

申请日：2023-11-02

Applicant: Texas Instruments Incorporated

Inventor： Robin Osa Hoel ,  Anand Kumar G ,  Dhivya Ravichandran ,  Aniruddha Periyapatna Nagendra

IPC: H03M13/09 ,  H03M13/00 ,  G06F13/40

CPC classification number: H03M13/091 ,  H03M13/611 ,  G06F13/40

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

公开(公告)号：US20240056092A1

公开(公告)日：2024-02-15

申请号：US18487234

申请日：2023-10-16

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G ,  Srinivasa BS Chakravarthy ,  Aniruddha Periyapatna Nagendra

IPC: H03M1/12

CPC classification number: H03M1/1225 ,  H03M1/1245

Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.

公开(公告)号：US20230163772A1

公开(公告)日：2023-05-25

申请号：US18159305

申请日：2023-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

公开(公告)号：US11592484B2

公开(公告)日：2023-02-28

申请号：US17165326

申请日：2021-02-02

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L9/40

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US20220412814A1

公开(公告)日：2022-12-29

申请号：US17355992

申请日：2021-06-23

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G

IPC: G01K7/42 ,  G06F12/16 ,  G01K1/022

Abstract: A temperature sensing device for a temperature-based tamper detection system includes an integrated circuit (IC) and a logic circuit. The logic circuit sends an enable signal to the IC, causing it to measure the device temperature, and initiates a security timer. In response to not receiving the device temperature before the security timer expires, the logic circuit outputs a tamper event signal and an error code. The logic circuit can disable the enable signal in response to not receiving the device temperature before the timer expires. In some implementations, the logic circuit is a first logic circuit, and the IC includes an analog integrated circuit (AIC) and a second logic circuit. The second logic circuit receives the enable signal from the first logic circuit, causes the AIC to measure the device temperature, and outputs a ready signal and the device temperature to the first logic circuit.

公开(公告)号：US20210156919A1

公开(公告)日：2021-05-27

申请号：US17165326

申请日：2021-02-02

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L29/06

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.