公开(公告)号：US20240297661A1

公开(公告)日：2024-09-05

申请号：US18258276

申请日：2021-11-04

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： YUKI YAGISHITA

IPC: H03M1/46 ,  H03M1/12

CPC classification number: H03M1/462 ,  H03M1/1245

Abstract: To reduce a circuit scale in a successive approximation register analog to digital converter (SARADC) provided with a circuit that cancels a ripple. A digital-to-analog converter generates at least one of a pair of analog signals according to a predetermined control signal. A comparator compares the pair of analog signals and outputs a comparison result. A logic circuit generates a control signal on the basis of the comparison result. A plurality of switches opens and closes a path between one of a source and a drain of each of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes and an output terminal of the comparator on the basis of the control signal. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected in common to each of the gates of the plurality of positive-side transistors. A negative-side capacitor has one end connected to a node of a negative-side reference voltage lower than the positive-side reference voltage, and has the other end connected in common to the gates of each of the plurality of negative-side transistors.

公开(公告)号：US12047097B2

公开(公告)日：2024-07-23

申请号：US17885126

申请日：2022-08-10

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Arashk Norouzpourshirazi ,  Stephen T. Hodapp ,  Ravi K. Kummaraguntla ,  Paul Wilson ,  Axel Thomsen

IPC: H03M3/00 ,  G11C27/02 ,  H02M3/07 ,  H03K17/06 ,  H03M1/12

CPC classification number: H03M3/496 ,  G11C27/024 ,  H02M3/07 ,  H03K17/063 ,  H03M1/1245 ,  H02M3/076

Abstract: A system may include a switched-capacitor analog front end comprising a plurality of switches for sampling an analog physical quantity and a bootstrap generation network electrically coupled to the plurality of switches and configured to generate a bootstrap sampling clock for controlling the plurality of switches and generate a floating supply voltage for the bootstrap sampling clock based on the analog physical quantity.

公开(公告)号：US20240235570A9

公开(公告)日：2024-07-11

申请号：US17971801

申请日：2022-10-24

Applicant: YUAN-JU CHAO

Inventor： YUAN-JU CHAO

IPC: H03M1/12

CPC classification number: H03M1/1245

Abstract: A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

公开(公告)号：US20240186962A1

公开(公告)日：2024-06-06

申请号：US18440255

申请日：2024-02-13

Applicant: EPIRUS, INC.

Inventor： Padraig James Cooney ,  Denpol Kultran ,  Ronald Chang ,  Harry Bourne Marr, JR.

IPC: H03F3/195 ,  H03F3/45 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03F3/195 ,  H03F3/45475 ,  H03M1/1245 ,  H03M1/462 ,  H03F2200/372 ,  H03F2200/451 ,  H03F2200/462

Abstract: An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock generator, a plurality of analog-to-digital converters, low and high-speed communications interfaces, drain and gate sensing circuits (that can include one or more current sense amplifiers), and a gate driver circuit. The ASIC can be a low voltage semiconductor integrated circuit.

公开(公告)号：US20240178855A1

公开(公告)日：2024-05-30

申请号：US18519144

申请日：2023-11-27

Applicant: IMEC VZW

Inventor： Nereo MARKULIC ,  Jan CRANINCKX

IPC: H03M1/12 ,  H03M1/06

CPC classification number: H03M1/1245 ,  H03M1/0614

Abstract: An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (Vin) and for outputting an output signal (Vout), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V21), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.

公开(公告)号：US20240169181A1

公开(公告)日：2024-05-23

申请号：US18239332

申请日：2023-08-29

Applicant: TDK CORPORATION

Inventor： Yukio TERASAKI

IPC: G06N3/044 ,  G06N3/063 ,  G06N5/04 ,  H03M1/12

CPC classification number: G06N3/044 ,  G06N3/063 ,  G06N5/04 ,  H03M1/1245

Abstract: A signal processor includes an input unit, an analog-digital converter, a control circuit, and a reservoir unit. The input unit receives a first analog signal. The analog-digital converter converts the first analog signal to a first digital signal. The control circuit detects the first analog signal or the first digital signal and outputs a control signal for extracting a part of the first analog signal or the first digital signal. The reservoir unit receives at least a part of the first digital signal and operates in synchronization with at least a part of the control signal.

公开(公告)号：US20240162913A1

公开(公告)日：2024-05-16

申请号：US18182071

申请日：2023-03-10

Applicant: SK hynix Inc.

Inventor： Se Won LEE

IPC: H03M1/12 ,  H03M1/18

CPC classification number: H03M1/1245 ,  H03M1/183

Abstract: A sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. The sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.

公开(公告)号：US20240128980A1

公开(公告)日：2024-04-18

申请号：US18186181

申请日：2023-03-19

Applicant: GIGADEVICE SEMICONDUCTOR INC.

Inventor： Sheng Liang

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/1205

Abstract: Disclosure regards a signal conversion device and method and an analog-to-digital converter, including a channel module including a plurality of sampling channels, wherein each of the plurality of sampling channels is configured to receive an analog signal; a timing-control module configured to provide a plurality of candidate sequences including a first sequence and a second sequence for the same sampling channel, wherein the timing-control module sets a first sampling time corresponding to the first sequence and a second sampling time corresponding to the second sequence; a conversion module electrically coupled to the timing-control module and the channel module, wherein the conversion module is configured to convert the analog signal from the same sampling channel into a digital signal in response to an order and sampling times defined by the candidate sequences. Therefore, problems of poor sampling accuracy and flexibility in the current sampling technologies are effectively solved.

公开(公告)号：US20240106450A1

公开(公告)日：2024-03-28

申请号：US18090997

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Rajashekar Goroju ,  Prasanth K ,  Dileepkumar Ramesh Bhat ,  Rahul Sharma

IPC: H03M1/12

CPC classification number: H03M1/1245

Abstract: An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.

公开(公告)号：US11916567B2

公开(公告)日：2024-02-27

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03M1/121

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.