中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

142 records (took 0.022 seconds)

    CMOS-based thermoelectric device with reduced electrical resistance
    51.
    发明授权
    CMOS-based thermoelectric device with reduced electrical resistance 有权
    具有降低电阻的CMOS基热电器件

    公开(公告)号：US09231025B2

    公开(公告)日：2016-01-05

    申请号：US14292119

    申请日：2014-05-30

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Kenneth James Maggio ,  Toan Tran ,  Jihong Chen ,  Jeffrey R. Debord

    IPC: H01L27/00 ,  H01L27/16 ,  H01L35/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L37/00

    CPC classification number: H01L35/34 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/10876 ,  H01L27/16 ,  H01L29/34 ,  H01L35/04 ,  H01L37/00 ,  H01L2924/13091

    Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

    Abstract translation: 可以通过在隔离沟槽中形成场氧化物来隔离嵌入式热电装置的CMOS晶体管和热电元件来形成包含CMOS晶体管和嵌入式热电装置的集成电路。 将N型掺杂剂注入到衬底中以在n型热电元件中提供至少1×1018cm-3n型掺杂剂和在n型热电元件之间的场氧化物下的衬底。 P型掺杂剂被注入到衬底中以在p型热电元件中提供至少1×1018cm-3p型掺杂剂，并且在p型热电元件之间的场氧化物之下提供衬底。 在形成场氧化物的隔离沟槽之后，在隔离沟槽中形成介电材料之前和/或在形成场氧化物之后，可以在形成场氧化物之前，注入n型掺杂剂和p型掺杂剂 。

    CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE
    52.
    发明申请
    CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE 有权
    具有降低热导率的CMOS基热电偶

    公开(公告)号：US20150349022A1

    公开(公告)日：2015-12-03

    申请号：US14292198

    申请日：2014-05-30

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

    IPC: H01L27/16 ,  H01L21/265 ,  H01L21/8238 ,  H01L35/04 ,  H01L27/092

    CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

    Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

    Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

    HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMICONDUCTOR MATERIAL
    53.
    发明申请
    HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMICONDUCTOR MATERIAL 有权

    公开(公告)号：US20250142876A1

    公开(公告)日：2025-05-01

    申请号：US19004098

    申请日：2024-12-27

    Applicant: Texas Instruments Incorporated

    Inventor： Christopher Boguslaw Kocon ,  Henry Litzmann Edwards ,  Curry Bachman Taylor

    IPC: H10D30/65 ,  H10D64/00

    Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

    Control of locos structure thickness without a mask
    57.
    发明授权
    Control of locos structure thickness without a mask 有权

    公开(公告)号：US11984362B1

    公开(公告)日：2024-05-14

    申请号：US17411761

    申请日：2021-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823462 ,  H01L27/088

    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

    Transistor device with buffered drain
    59.
    发明授权
    Transistor device with buffered drain 有权

    公开(公告)号：US11876134B2

    公开(公告)日：2024-01-16

    申请号：US17489513

    申请日：2021-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry Litzmann Edwards

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/7824 ,  H01L29/0852 ,  H01L29/1033 ,  H01L29/66681

    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

    Transistors with oxide liner in drift region
    60.
    发明授权
    Transistors with oxide liner in drift region 有权

    公开(公告)号：US11552183B2

    公开(公告)日：2023-01-10

    申请号：US16897382

    申请日：2020-06-10

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Andrew D. Strachan

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266 ,  H01L29/40

    Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

Patent Agency Ranking