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    Tap linking module, first and second taps, input/output linking circuitry
    51.
    发明授权
    Tap linking module, first and second taps, input/output linking circuitry 有权

    公开(公告)号：US10267855B2

    公开(公告)日：2019-04-23

    申请号：US15783365

    申请日：2017-10-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    Tap, decoder providing SC and SE to scan path circuits
    52.
    发明授权
    Tap, decoder providing SC and SE to scan path circuits 有权

    公开(公告)号：US10247779B2

    公开(公告)日：2019-04-02

    申请号：US15901398

    申请日：2018-02-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3183 ,  G01R31/3185 ,  G06F11/273 ,  G01R31/3177 ,  G01R31/317

    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

    IC TAP, SAP state machine stepping on TCK falling edge
    54.
    发明授权
    IC TAP, SAP state machine stepping on TCK falling edge 有权

    公开(公告)号：US10215805B2

    公开(公告)日：2019-02-26

    申请号：US16037649

    申请日：2018-07-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

    Test compression in a JTAG daisy-chain environment
    55.
    发明授权
    Test compression in a JTAG daisy-chain environment 有权

    公开(公告)号：US10209304B2

    公开(公告)日：2019-02-19

    申请号：US15945414

    申请日：2018-04-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

    Tap flip flop, gate, and compare circuitry on rising SCK
    58.
    发明授权
    Tap flip flop, gate, and compare circuitry on rising SCK 有权

    公开(公告)号：US10120022B2

    公开(公告)日：2018-11-06

    申请号：US15467517

    申请日：2017-03-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

    Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

    DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
    60.
    发明申请
    DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM 审中-公开

    公开(公告)号：US20180292455A1

    公开(公告)日：2018-10-11

    申请号：US16003858

    申请日：2018-06-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318563

    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

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