公开(公告)号：US07563659B2

公开(公告)日：2009-07-21

申请号：US11003326

申请日：2004-12-06

Applicant: Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

Inventor： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC: H01L21/00

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using inductively coupled plasma chemical vapor deposition (ICP-CVD). After the ICP-CVD, excimer laser annealing (ELA) is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO2 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiO2 can be as high as 1011/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

Abstract translation: 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用电感耦合等离子体化学气相沉积（ICP-CVD）在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时进行准分子激光退火（ELA）。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2栅极绝缘层。 多晶硅的大晶粒尺寸约为3000或更大。 SiO2的界面陷阱密度高达1011 / cm2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US07560317B2

公开(公告)日：2009-07-14

申请号：US11493182

申请日：2006-07-26

Applicant: Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Hans S. Cho ,  Kyung-bae Park

Inventor： Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Hans S. Cho ,  Kyung-bae Park

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/02639 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667 ,  H01L27/1281 ,  H01L29/66772

Abstract: Provided are a method of forming a single crystalline silicon layer, a structure including the same, and method of fabricating a thin film transistor (“TFT”) using the same. The method of forming the single crystalline silicon layer includes forming a silicon nitride layer on a substrate, forming an insulating layer on the silicon nitride layer, forming a hole in the insulating layer to a predetermined dimension, depositing a first silicon layer on an exposed bottom of the hole using a selective deposition process, depositing a second silicon layer on the insulating layer and the first silicon layer formed in the hole, and crystallizing the second silicon layer using a thermal process. In this method, a high-quality single crystalline silicon layer can be obtained.

Abstract translation: 提供了形成单晶硅层的方法，包括其的结构，以及使用其制造薄膜晶体管（“TFT”）的方法。 形成单晶硅层的方法包括在衬底上形成氮化硅层，在氮化硅层上形成绝缘层，在绝缘层中形成预定尺寸的孔，在暴露的底部上沉积第一硅层 使用选择性沉积工艺，在绝缘层上沉积第二硅层和在孔中形成的第一硅层，并使用热处理使第二硅层结晶。 在该方法中，可以获得高品质的单晶硅层。

公开(公告)号：US07557411B2

公开(公告)日：2009-07-07

申请号：US11397866

申请日：2006-04-05

Applicant: Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin ,  Xiaoxin Zhang

Inventor： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/392

CPC classification number: H01L29/78687 ,  H01L29/66742 ,  H01L29/78603

Abstract: Semiconductor-on-insulator (SOI) structures, semiconductor devices using the same and methods of manufacturing the same, and more particularly, to a structure with a single-crystalline (for example, germanium (x-Ge)) layer on an insulating layer, semiconductor devices using the same, and methods of manufacturing the same. The SOI structure may include a single-crystalline substrate formed of a first semiconductor material, a first insulating layer formed on the substrate and having at least one window exposing a portion of the substrate, a first epitaxial growth region formed on a surface of the substrate exposed by the window and formed of at least one of the first semiconductor material and a second semiconductor material, and a first single-crystalline layer formed on the first insulating layer and the first epitaxial growth region and formed of the second semiconductor material, and crystallized using a surface of the first epitaxial growth region as a seed layer for crystallization.

Abstract translation: 绝缘体上半导体（SOI）结构，使用其的半导体器件及其制造方法，更具体地说，涉及在绝缘层上具有单晶（例如锗（x-Ge））层的结构 ，使用其的半导体器件及其制造方法。 SOI结构可以包括由第一半导体材料形成的单晶衬底，形成在衬底上的第一绝缘层，并且具有暴露衬底的一部分的至少一个窗口，形成在衬底表面上的第一外延生长区域 由窗口露出并由第一半导体材料和第二半导体材料中的至少一个形成，以及形成在第一绝缘层和第一外延生长区上并由第二半导体材料形成的第一单晶层，并且晶化 使用第一外延生长区域的表面作为晶种层进行结晶。

公开(公告)号：US07544585B2

公开(公告)日：2009-06-09

申请号：US12003039

申请日：2007-12-19

Applicant: Young-soo Park ,  Wenxu Xianyu ,  Takashi Noguchi

Inventor： Young-soo Park ,  Wenxu Xianyu ,  Takashi Noguchi

IPC: H01L21/30

CPC classification number: H01L21/76259 ,  H01L21/32134 ,  H01L21/76256 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78687 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

Abstract: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.

Abstract translation: 提供了应变SOI结构和制造应变SOI结构的方法。 应变SOI结构包括绝缘衬底，形成在绝缘衬底上的SiO 2层和形成在SiO 2层上的应变硅层。

公开(公告)号：US07540019B2

公开(公告)日：2009-05-26

申请号：US10998751

申请日：2004-11-30

Applicant: Takashi Noguchi ,  Takayuki Noda ,  Hiromitsu Kato ,  Katsumi Kawano

Inventor： Takashi Noguchi ,  Takayuki Noda ,  Hiromitsu Kato ,  Katsumi Kawano

IPC: H04L9/00

CPC classification number: G06F21/35 ,  G06F21/32 ,  G06F21/6254

Abstract: A processing device has a personal authentication information receiving unit for receiving personal authentication information, a security information DB, and a processing information managing unit. The processing information managing unit converts the personal authentication information received by the personal authentication receiving unit to a user ID, detects an event concerning a processing operation, and associates the event with the user ID, thereby creating or updating an access management table for processing performance information, for storage in the security information DB. The processing information management unit then controls access to the processing performance information based on the access management table and the user ID obtained by conversion of the personal authentication information received by the personal authentication information receiving unit.

Abstract translation: 处理装置具有用于接收个人认证信息的个人认证信息接收单元，安全信息DB和处理信息管理单元。 处理信息管理单元将由个人认证接收单元接收的个人认证信息转换为用户ID，检测与处理操作有关的事件，并将事件与用户ID相关联，从而创建或更新用于处理性能的访问管理表 信息，用于存储在安全信息DB中。 处理信息管理单元然后基于由个人认证信息接收单元接收的个人认证信息的转换而获得的访问管理表和用户ID来控制对处理性能信息的访问。

公开(公告)号：US07482648B2

公开(公告)日：2009-01-27

申请号：US11024469

申请日：2004-12-30

Applicant: Wenxu Xianyu ,  Takashi Noguchi ,  In-kyeong Yoo ,  Young-soo Park

Inventor： Wenxu Xianyu ,  Takashi Noguchi ,  In-kyeong Yoo ,  Young-soo Park

IPC: H01L31/119

CPC classification number: H01L27/11507 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/12

Abstract: In an electronic device, and a method of manufacturing the same, the electronic device includes a first substrate, a first lower capacitor on the first substrate, a first lower switching element on the first lower capacitor, and a second substrate on the first lower switching element. The electronic device may further include a second lower switching element which is isolated from the first lower capacitor, and an upper capacitor on the second substrate, the lower electrode of the upper capacitor being connected to the second lower switching element.

Abstract translation: 在电子设备及其制造方法中，电子设备包括第一基板，第一基板上的第一下部电容器，第一下部电容器上的第一下部开关元件，以及第一下部开关 元件。 电子设备还可以包括与第一下电容器隔离的第二下开关元件和第二基板上的上电容器，上电容器的下电极连接到第二下开关元件。

公开(公告)号：US07414264B2

公开(公告)日：2008-08-19

申请号：US11022766

申请日：2004-12-28

Applicant: Do-young Kim ,  Takashi Noguchi

Inventor： Do-young Kim ,  Takashi Noguchi

IPC: H01L31/00 ,  H01L21/00 ,  G02F1/136

CPC classification number: H01L27/124 ,  H01L29/42384

Abstract: Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

Abstract translation: 提供一种多晶硅半导体器件及其制造方法。 除去栅极以外的硅层的部分被去除以减少由存在于栅极总线上的硅层引起的寄生电容。 硅层仅存在于栅极之下，因此寄生电容减小，并且防止信号的劣化和延迟。 因此，诸如薄膜晶体管的多晶硅半导体器件具有优异的电特性。

公开(公告)号：US07309838B2

公开(公告)日：2007-12-18

申请号：US10891127

申请日：2004-07-15

Applicant: Takashi Noguchi

Inventor： Takashi Noguchi

IPC: H05K1/03

CPC classification number: H05K1/185 ,  H01L23/3672 ,  H01L23/3737 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0207 ,  H05K3/4069 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0919 ,  H01L2924/00

Abstract: A circuit board assembly includes an electrical component mounted on or in the assembly; a conductive layer, which is electrically connected to the electrical component; a high-temperature dissipation resin, which is of insulating material and is arranged so as to dissipate heat generated in the assembly; and a molding resin surrounding the electrical component. Heat, generated at electrical components in a circuit board assembly, is transferred and dispersed through the high-temperature dissipation material all over the assembly. Further, since the high-temperature dissipation resin is of an insulating material, it is unnecessary to consider a short-circuit problem in the assembly.

Abstract translation: 电路板组件包括安装在组件上或组件中的电气部件; 导电层，其电连接到电气部件; 高温耗散树脂，其是绝缘材料并且布置成散发在组件中产生的热量; 以及围绕电气部件的成型树脂。 在电路板组件中的电气部件产生的热量通过整个组件中的高温耗散材料传递和分散。 此外，由于高温耗散树脂是绝缘材料，因此不需要考虑组装中的短路问题。

公开(公告)号：US07303979B2

公开(公告)日：2007-12-04

申请号：US10818821

申请日：2004-04-06

Applicant: Hideo Yamagata ,  Takeyoshi Koumoto ,  Kenji Atsuumi ,  Yoichi Negoro ,  Tatsushiro Hirata ,  Takashi Noguchi

Inventor： Hideo Yamagata ,  Takeyoshi Koumoto ,  Kenji Atsuumi ,  Yoichi Negoro ,  Tatsushiro Hirata ,  Takashi Noguchi

IPC: H01L21/322

CPC classification number: H01L21/02505 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66242

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer. Thus, there can be obtained a semiconductor layer in which a misfit dislocation can be improved.

Abstract translation: 在半导体基板上沉积硅 - 锗混晶层的气相生长方法中，气相生长方法包括将硅原料气体引入反应炉的第一步骤，即将硅 原料气体分压与时间成比例地增加，从而在半导体衬底上沉积硅层的第一半导体层减压，第二步是将硅原料气体和锗原料气体引入反应炉中 可以获得期望的锗浓度，从而在减压下在第一半导体层上沉积硅 - 锗混合晶体层的第二半导体层，并且在减压下将硅原料气体引入反应炉中的第三步骤 从而在第二半导体层上沉积硅层的第三半导体层。 因此，可以获得其中可以提高失配位错的半导体层。

公开(公告)号：US07297615B2

公开(公告)日：2007-11-20

申请号：US11341519

申请日：2006-01-30

Applicant: Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

Inventor： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC: C30B1/02 ,  H01L21/20

CPC classification number: H01L29/78654 ,  H01L29/0673 ,  H01L29/66772 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/938 ,  Y10T428/26

Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.