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公开(公告)号:US20180116078A1
公开(公告)日:2018-04-26
申请号:US15789184
申请日:2017-10-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Il-ju MUN , Keon KUK , Ji-woon YEOM
IPC: H05K9/00 , H05K1/11 , H05K1/18 , H01L23/552 , H05K3/40
CPC classification number: H05K9/0024 , H01L23/552 , H05K1/111 , H05K1/117 , H05K1/181 , H05K3/284 , H05K3/321 , H05K3/4007 , H05K9/0039 , H05K2201/0919 , H05K2201/10371 , H05K2201/10522 , H05K2201/10545 , H05K2201/10734 , H05K2203/0126 , H05K2203/1316 , H05K2203/1327 , H05K2203/163
Abstract: An EMI shielding structure includes a shielding pad surrounding at least one circuit component mounted on a printed circuit board and grounded to a ground pad disposed on the printed circuit board; and a shield can configured to cover the at least one circuit component, wherein a portion of the shield can is attached to the shielding pad.
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公开(公告)号:US09774070B2
公开(公告)日:2017-09-26
申请号:US14537059
申请日:2014-11-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Nobuo Ikemoto , Yuki Wakabayashi , Shigeru Tago
IPC: H01P3/08 , H01P11/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K3/36 , H01R12/62 , H05K3/00 , H05K3/46 , H01R103/00 , H01R24/50
CPC classification number: H01P3/082 , H01P3/08 , H01P11/003 , H01R12/62 , H01R24/50 , H01R2103/00 , H05K1/0219 , H05K1/0225 , H05K1/024 , H05K1/0242 , H05K1/0253 , H05K1/115 , H05K1/118 , H05K1/147 , H05K3/0052 , H05K3/363 , H05K3/4623 , H05K3/4632 , H05K2201/07 , H05K2201/09154 , H05K2201/0919 , H05K2201/09481 , H05K2201/09527 , H05K2201/096 , H05K2201/09618 , H05K2201/097 , H05K2201/09845 , H05K2201/10037 , H05K2201/10204 , Y10T29/49016
Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.
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公开(公告)号:US09693460B2
公开(公告)日:2017-06-27
申请号:US14017849
申请日:2013-09-04
Applicant: OLYMPUS CORPORATION
Inventor: Noriyuki Fujimori
IPC: H05K1/00 , H05K1/18 , A61B1/05 , H04N5/225 , H05K3/40 , H05K3/10 , A61B1/00 , H05K3/00 , H05K3/46
CPC classification number: H05K1/181 , A61B1/0011 , A61B1/051 , H04N5/2251 , H05K1/18 , H05K1/186 , H05K3/0052 , H05K3/10 , H05K3/403 , H05K3/4602 , H05K2201/0919 , H05K2201/10121 , H05K2201/10356 , H05K2201/10416 , H05K2201/10446 , Y10T29/49162
Abstract: A wiring board includes a plurality of wiring layers, a plurality of insulating layers, and an electrode member made of a conductive material, the electrode member being incorporated in the wiring board in a state in which the electrode member includes exposed sections on side surfaces that cross the plurality of wiring layers and the plurality of insulating layers.
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公开(公告)号:US09679865B2
公开(公告)日:2017-06-13
申请号:US14253554
申请日:2014-04-15
Applicant: SK hynix Inc.
Inventor: Eun Hye Do
CPC classification number: H01L24/49 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48228 , H01L2224/49 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2924/00014 , H01L2924/1517 , H01L2924/15313 , H05K3/341 , H05K3/4015 , H05K3/4697 , H05K2201/0919 , H05K2201/09845 , H05K2201/10159 , H05K2201/10287 , H05K2201/10515 , Y02P70/613 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
Abstract: A semiconductor package includes a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.
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公开(公告)号:US20170117636A1
公开(公告)日:2017-04-27
申请号:US15400762
申请日:2017-01-06
Applicant: Keyssa, Inc.
Inventor: Emilio Sovero , Gary D. McCormack
CPC classification number: H01Q13/103 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01P3/006 , H01P3/121 , H01Q1/24 , H01Q1/38 , H01Q1/48 , H01Q7/00 , H05K1/0218 , H05K1/0274 , H05K2201/0191 , H05K2201/0919 , H05K2201/09618 , H05K2201/09845 , H05K2201/2036 , H01L2924/00012 , H01L2924/00
Abstract: A system for transmitting or receiving signals may include a dielectric substrate having a major face, a communication circuit, and an electromagnetic-energy directing assembly. The circuit may include a transducer configured to convert between RF electrical and RF electromagnetic signals and supported in a position spaced from the major face of the substrate operatively coupled to the transducer. The directing assembly may be supported by the substrate in spaced relationship from the transducer and configured to direct EM energy in a region including the transducer and along a line extending away from the transducer and transverse to a plane of the major face.
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公开(公告)号:US09629248B2
公开(公告)日:2017-04-18
申请号:US14613854
申请日:2015-02-04
Applicant: LG INNOTEK CO., LTD.
Inventor: Deok Soon Kwon , Sang Hyuck Nam , Won Suk Jung
IPC: H05K1/18 , H05K1/02 , H05K3/00 , H05K3/46 , H05K3/02 , H05K3/28 , H01L21/56 , H01L23/00 , H01L27/146
CPC classification number: H05K1/184 , H01L21/568 , H01L24/19 , H01L24/20 , H01L27/14618 , H01L2224/04105 , H05K1/0268 , H05K1/188 , H05K3/0035 , H05K3/0047 , H05K3/025 , H05K3/282 , H05K3/4626 , H05K3/4697 , H05K2201/068 , H05K2201/0919 , H05K2201/10151 , H05K2203/063 , H05K2203/1383 , H05K2203/1388 , H05K2203/1469 , H05K2203/162
Abstract: Provided is an embedded printed circuit board, including: a first insulating substrate including a first cavity and a second cavity; a first element disposed in the first cavity; an adhesive layer for adhering the first insulating substrate to the first element and including an opening to which the first element is exposed; and an second insulating substrate forming a bonding layer of a lower surface of the first insulating substrate and a bottom surface of the second cavity.
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公开(公告)号:US09508634B2
公开(公告)日:2016-11-29
申请号:US15133244
申请日:2016-04-20
Applicant: IBIS Innotech Inc.
Inventor: Wen-Chun Liu
IPC: H05K7/10 , H05K7/12 , H01L23/495 , H01L21/768 , H05K1/03 , H05K3/18 , H05K3/40 , H05K1/11 , H05K3/00 , H05K3/10 , H05K3/46
CPC classification number: H01L23/49586 , H01L21/4828 , H01L21/76823 , H01L21/76825 , H01L23/13 , H01L23/4952 , H01L23/49541 , H01L23/49558 , H01L23/49861 , H01L2224/48091 , H01L2924/181 , H05K1/0373 , H05K1/113 , H05K3/0014 , H05K3/105 , H05K3/188 , H05K3/4007 , H05K3/4697 , H05K2201/0236 , H05K2201/0376 , H05K2201/09063 , H05K2201/09118 , H05K2201/0919 , H05K2201/10151 , H05K2201/10515 , H05K2201/10674 , H01L2924/00012 , H01L2924/00014
Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.
Abstract translation: 封装结构包括引线框,选择性电镀环氧化合物,导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中,以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段,并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。
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公开(公告)号:US09445497B2
公开(公告)日:2016-09-13
申请号:US14793256
申请日:2015-07-07
Applicant: Mitsubishi Electric Corporation
Inventor: Daisuke Oya , Tatsuya Iwasa
CPC classification number: H05K1/0306 , H01L2224/0603 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2924/19107 , H05K1/0296 , H05K1/142 , H05K1/181 , H05K3/0067 , H05K2201/0919 , H05K2201/09845 , H01L2924/00014
Abstract: A semiconductor device includes a first ceramic substrate, a second ceramic substrate, an inter-ceramic metal having an intermediate portion interposed between an upper surface of the first ceramic substrate and a lower surface of the second ceramic substrate, a first surmounting portion formed on an upper surface of the second ceramic substrate, a second surmounting portion formed on the upper surface of the second ceramic substrate, a first connection portion abutting on an outer edge of the second ceramic substrate and connecting the intermediate portion and the first surmounting portion, and a second connection portion abutting on an outer edge of the second ceramic substrate and connecting the intermediate portion and the second surmounting portion, a circuit pattern formed on the second ceramic substrate, and a semiconductor element provided on the circuit pattern.
Abstract translation: 半导体器件包括第一陶瓷衬底,第二陶瓷衬底,陶瓷间陶瓷金属,其中间部分介于第一陶瓷衬底的上表面和第二陶瓷衬底的下表面之间,第一超支撑部分形成在第一陶瓷衬底 第二陶瓷基板的上表面,形成在第二陶瓷基板的上表面上的第二超越部分,与第二陶瓷基板的外边缘抵接并连接中间部分和第一超越部分的第一连接部分, 第二连接部分邻接在第二陶瓷基板的外边缘上并连接中间部分和第二超越部分,形成在第二陶瓷基板上的电路图案和设置在电路图案上的半导体元件。
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公开(公告)号:US20160242331A1
公开(公告)日:2016-08-18
申请号:US15045841
申请日:2016-02-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Sik PARK , Seung-Ki CHOI , Joon HEO , Hyun-Ju HONG
CPC classification number: H05K9/002 , H01L2224/16225 , H05K1/0218 , H05K1/0259 , H05K5/0004 , H05K5/0017 , H05K9/0024 , H05K9/0039 , H05K2201/0919 , H05K2201/09354 , H05K2201/10371
Abstract: An electronic device is provided that includes a PCB including a first surface, a second surface, and a side surface; an electronic component arranged on the first surface, adjacent to a portion of the side surface; a shield structure including a cap that covers the electronic component and a sidewall extending from a periphery of the cap toward the first surface of the PCB, wherein the sidewall extends in a first direction that is non-parallel to the first surface of the PCB; a first conductive structure that is formed on a portion of the side surface of the PCB; and a second conductive structure that is formed on a portion of the first surface to be connected to the first conductive structure. The sidewall contacts with the first surface of the PCB and overlaps with the second conductive structure, when viewed from above the first surface of the PCB.
Abstract translation: 提供一种电子设备,其包括:PCB,其包括第一表面,第二表面和侧表面; 布置在所述第一表面上的与所述侧表面的一部分相邻的电子部件; 屏蔽结构,其包括覆盖电子部件的盖和从盖的周边延伸到PCB的第一表面的侧壁,其中侧壁沿不平行于PCB的第一表面的第一方向延伸; 第一导电结构,其形成在所述PCB的侧表面的一部分上; 以及形成在所述第一表面的要连接到所述第一导电结构的部分上的第二导电结构。 当从PCB的第一表面上方观察时,侧壁与PCB的第一表面接触并与第二导电结构重叠。
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公开(公告)号:US09287224B2
公开(公告)日:2016-03-15
申请号:US14090560
申请日:2013-11-26
Applicant: FUJITSU LIMITED
Inventor: Satoshi Masuda
IPC: H01L23/34 , H01L23/66 , H01L25/16 , H01L23/045 , H01L23/047 , H01L23/498 , H05K3/46 , H05K7/20 , H01L23/00 , H01L23/367 , H05K1/02 , H05K9/00
CPC classification number: H05K7/026 , H01L23/045 , H01L23/047 , H01L23/3677 , H01L23/49833 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/162 , H01L2224/06181 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2924/00014 , H01L2924/16195 , H01L2924/1627 , H01L2924/19107 , H05K1/0204 , H05K1/021 , H05K1/0215 , H05K3/4697 , H05K7/20509 , H05K9/0039 , H05K2201/0919 , H05K2201/09845 , H05K2201/10242 , H05K2201/10371 , H05K2201/1056 , H01L2224/45099
Abstract: A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate.
Abstract translation: 高频模块包括下基部件,其具有形成在其上表面中的凹部,并且具有形成在其下表面上的待接地的基底金属部分,设置在下部的凹部内的上基板 基底构件,安装在上基板的上表面上的半导体器件,连接到半导体器件并形成在上基板上的第一接地线,以及连接到基底金属部分并设置在下基底构件中的接地金属部件 ,其中所述接地金属部分连接到所述上基板上的所述第一接地线。
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