公开(公告)号：US09490341B2

公开(公告)日：2016-11-08

申请号：US14704994

申请日：2015-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。

公开(公告)号：US09466564B1

公开(公告)日：2016-10-11

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L23/522 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US20160276260A1

公开(公告)日：2016-09-22

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

Abstract translation: 公开了一种用于制造金属互连结构的方法。 该方法包括以下步骤：提供其上具有第一金属间电介质（IMD）层的衬底; 在第一IMD层中形成金属互连; 去除第一IMD层的一部分; 形成邻近所述金属互连的间隔物; 并且使用间隔物作为掩模来去除第一IMD层的一部分，以在第一IMD层中形成开口。

公开(公告)号：US20150287823A1

公开(公告)日：2015-10-08

申请号：US14275858

申请日：2014-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/49 ,  H01L21/265 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。

公开(公告)号：US20150214060A1

公开(公告)日：2015-07-30

申请号：US14680078

申请日：2015-04-07

Applicant: United Microelectronics Corp.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US20240204085A1

公开(公告)日：2024-06-20

申请号：US18105798

申请日：2023-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02293 ,  H01L29/42312 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.

公开(公告)号：US11482517B2

公开(公告)日：2022-10-25

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L21/3213 ,  H01L27/11582 ,  H01L49/02

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US10460997B2

公开(公告)日：2019-10-29

申请号：US16360019

申请日：2019-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/14 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/08 ,  H01L21/82 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US10396171B2

公开(公告)日：2019-08-27

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US20190221482A1

公开(公告)日：2019-07-18

申请号：US16360019

申请日：2019-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/8213 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.