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    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF
    51.
    发明申请
    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20250048944A1

    公开(公告)日：2025-02-06

    申请号：US18237915

    申请日：2023-08-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, and a resistive switching structure embedded in an upper portion of the conductive via. The resistive switching structure includes a top electrode layer having a lower sharp corner, a resistive switching material layer disposed around the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistive switching material layer and the upper portion of the conductive via.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    54.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220359618A1

    公开(公告)日：2022-11-10

    申请号：US17870814

    申请日：2022-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

    Resistive random-access memory (RRAM) device and forming method thereof
    55.
    发明授权
    Resistive random-access memory (RRAM) device and forming method thereof 有权

    公开(公告)号：US11489114B2

    公开(公告)日：2022-11-01

    申请号：US17211875

    申请日：2021-03-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00

    Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.

    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND FORMING METHOD THEREOF
    56.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220209112A1

    公开(公告)日：2022-06-30

    申请号：US17159160

    申请日：2021-01-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.

    Resistive random access memory structure and method for manufacturing the same
    58.
    发明授权
    Resistive random access memory structure and method for manufacturing the same 有权

    公开(公告)号：US11094880B2

    公开(公告)日：2021-08-17

    申请号：US16504491

    申请日：2019-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

    Memory structure and manufacturing method thereof
    59.
    发明授权
    Memory structure and manufacturing method thereof 有权

    公开(公告)号：US10770565B2

    公开(公告)日：2020-09-08

    申请号：US16123868

    申请日：2018-09-06

    Applicant: United Microelectronics Corp.

    Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/45 ,  H01L29/49

    Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

    Semiconductor memory device and fabrication method thereof
    60.
    发明授权
    Semiconductor memory device and fabrication method thereof 有权

    公开(公告)号：US10608006B2

    公开(公告)日：2020-03-31

    申请号：US16038197

    申请日：2018-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

    Abstract: A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.

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