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公开(公告)号：US20210028351A1
公开(公告)日：2021-01-28
申请号：US17064607
申请日：2020-10-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang
Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).
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公开(公告)号：US20200266335A1
公开(公告)日：2020-08-20
申请号：US16297704
申请日：2019-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
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公开(公告)号：US20200227625A1
公开(公告)日：2020-07-16
申请号：US16261524
申请日：2019-01-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yi-Wei Tseng , Meng-Jun Wang , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang , Yu-Ping Wang , Chien-Ting Lin , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , I-Ming Tseng
Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
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公开(公告)号：US12290005B2
公开(公告)日：2025-04-29
申请号：US18679437
申请日：2024-05-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20250107454A1
公开(公告)日：2025-03-27
申请号：US18976359
申请日：2024-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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Patent Agency Ranking
公开(公告)号：US12262647B2
公开(公告)日：2025-03-25
申请号：US18592553
申请日：2024-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
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公开(公告)号：US12133474B2
公开(公告)日：2024-10-29
申请号：US18373295
申请日：2023-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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公开(公告)号：US20240324472A1
公开(公告)日：2024-09-26
申请号：US18679437
申请日：2024-05-30
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20240268124A1
公开(公告)日：2024-08-08
申请号：US18636306
申请日：2024-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
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公开(公告)号：US12029044B2
公开(公告)日：2024-07-02
申请号：US18127651
申请日：2023-03-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
CPC classification number: H10B61/00 , G11C11/161 , H10B61/10 , H10N50/01 , H10N50/80
Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
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