公开(公告)号：US20230163184A1

公开(公告)日：2023-05-25

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  JINYU LIAO

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/41758 ,  H01L29/0653 ,  H01L21/823418 ,  H01L21/823481

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

公开(公告)号：US20220415831A1

公开(公告)日：2022-12-29

申请号：US17383290

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

公开(公告)号：US20220216345A1

公开(公告)日：2022-07-07

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20210210605A1

公开(公告)日：2021-07-08

申请号：US17191720

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Su Xing

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66

Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

公开(公告)号：US20210175371A1

公开(公告)日：2021-06-10

申请号：US16739022

申请日：2020-01-09

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

公开(公告)号：US20190103408A1

公开(公告)日：2019-04-04

申请号：US16207171

申请日：2018-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/78648

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US10153342B1

公开(公告)日：2018-12-11

申请号：US15794065

申请日：2017-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Xun He ,  Kui Mei ,  Su Xing

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08

Abstract: A semiconductor device includes a substrate; an active layer disposed over the substrate and having a source region and a drain region; a contact region disposed over the substrate; a gate structure disposed over the active layer, wherein the gate structure includes a middle portion and a lateral portion connecting to the middle portion, and the lateral portion has a snake shape.

公开(公告)号：US10062734B2

公开(公告)日：2018-08-28

申请号：US15849563

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L21/8234 ,  H01L45/00 ,  H01L27/24 ,  H01L29/786

CPC classification number: H01L21/82345 ,  H01L29/435 ,  H01L29/4908 ,  H01L29/7869

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer near one side of the gate dielectric layer and a drain layer near another side of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

公开(公告)号：US10008614B1

公开(公告)日：2018-06-26

申请号：US15464353

申请日：2017-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L29/1054 ,  H01L29/41733 ,  H01L29/78648 ,  H01L29/7869

Abstract: A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.

公开(公告)号：US20180102434A1

公开(公告)日：2018-04-12

申请号：US15709450

申请日：2017-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/78 ,  H01L29/24 ,  H01L21/467 ,  H01L21/441 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/441 ,  H01L21/467 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.