公开(公告)号：US20180122897A1

公开(公告)日：2018-05-03

申请号：US15365954

申请日：2016-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/0649 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

公开(公告)号：US20180269212A1

公开(公告)日：2018-09-20

申请号：US15491939

申请日：2017-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US20190103408A1

公开(公告)日：2019-04-04

申请号：US16207171

申请日：2018-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/78648

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US20180102434A1

公开(公告)日：2018-04-12

申请号：US15709450

申请日：2017-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/78 ,  H01L29/24 ,  H01L21/467 ,  H01L21/441 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/441 ,  H01L21/467 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.

公开(公告)号：US20190109200A1

公开(公告)日：2019-04-11

申请号：US15802419

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/49 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L29/4933 ,  H01L23/66 ,  H01L29/0607 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78651

Abstract: A radiofrequency switch device includes an insulation layer, a semiconductor layer, a gate structure, a first doped region, a second doped region, an epitaxial layer, a first silicide layer, and a second silicide layer. The semiconductor layer is disposed on the insulation layer. The gate structure is disposed on the semiconductor layer. The first doped region and the second doped region are disposed in the semiconductor layer at two opposite sides of the gate structure respectively. The epitaxial layer is disposed on the first doped region. The first silicide layer is disposed on the epitaxial layer. The second silicide layer is disposed in the second doped region.

公开(公告)号：US20180190714A1

公开(公告)日：2018-07-05

申请号：US15849563

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L27/2436 ,  H01L21/82345 ,  H01L29/7869 ,  H01L45/065 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

公开(公告)号：US20180145081A1

公开(公告)日：2018-05-24

申请号：US15361070

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1116

Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.