公开(公告)号：US20120221884A1

公开(公告)日：2012-08-30

申请号：US13036826

申请日：2011-02-28

Applicant: Nicholas P. Carter ,  Donald S. Gardner ,  Eric C. Hannah ,  Helia Naeimi ,  Shekhar Y. Borkar ,  Matthew Haycock

Inventor： Nicholas P. Carter ,  Donald S. Gardner ,  Eric C. Hannah ,  Helia Naeimi ,  Shekhar Y. Borkar ,  Matthew Haycock

IPC: G06F11/07

CPC classification number: G06F11/0781 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1425 ,  G06F11/1428

Abstract: Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.

Abstract translation: 通常，本公开提供跨越硬件和软件层的错误管理，以使硬件和软件能够在由于老化，制造公差等导致的错误和硬件变化的情况下提供可靠的操作。在一个实施例中，提供了一种错误管理模块， 来自硬件和软件层的信息，并检测和诊断错误。 可以选择硬件或软件恢复技术来提供有效的操作，并且在一些实施例中，硬件设备可以被重新配置以防止将来的错误，并允许硬件设备在永久性错误的情况下操作。

公开(公告)号：US20120126851A1

公开(公告)日：2012-05-24

申请号：US13216193

申请日：2011-08-23

Applicant: Steven Hennick Kelem ,  Brian A. Box ,  John M. Rudosky ,  Stephen L. Wasson

Inventor： Steven Hennick Kelem ,  Brian A. Box ,  John M. Rudosky ,  Stephen L. Wasson

IPC: H03K19/173

CPC classification number: H03K19/173 ,  G06F9/3897 ,  G06F11/1423 ,  G06F11/1428 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/17756

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.

Abstract translation: 示例性实施例提供可重构集成电路架构，其包括：可配置用于多个数据操作的可配置电路元件，每个数据操作对应于多个上下文的上下文; 多个输入队列; 多个输出队列; 一个或多个配置和控制寄存器，用于为多个上下文的每个上下文存储指定至少一个数据输入队列和至少一个数据输出队列的多个配置位，运行状态位和多个位; 以及耦合到所述可配置电路元件和所述一个或多个配置和控制寄存器的元件控制器，所述元件控制器允许在上下文指定的数据输入中输入数据到达时加载上下文配置和执行数据操作 上下文运行状态被启用并且上下文指定的数据输出队列具有接受输出数据的状态时的队列。

公开(公告)号：US06973608B1

公开(公告)日：2005-12-06

申请号：US10189640

申请日：2002-07-03

Applicant: Miron Abramovici ,  John M. Emmert ,  Charles E. Stroud

Inventor： Miron Abramovici ,  John M. Emmert ,  Charles E. Stroud

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  H03K19/177

CPC classification number: H03K19/17752 ,  G06F11/142 ,  G06F11/1428 ,  H03K19/17756 ,  H03K19/17764

Abstract: A method of fault tolerant operation of field programmable gate arrays (FPGAs), whether as an embedded portion of a system-on-chip or other application specific integrated circuit, utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into a self-testing area and a working area. Within the self-testing area, programmable interconnect resources of the FPGA are tested for faults. Upon the detection of one or more faults within the interconnect resources, the faulty interconnect resources are identified and a determination is made whether utilization of the faulty interconnect resources is compatible with an intended operation of the FPGAs. If the faulty interconnect resources are compatible with the intended operation of the FPGA, utilization of the faulty interconnect resource is allowed to provide fault tolerant operation of the FPGA. If the faulty interconnect resources are not compatible with the intended operation of the FPGA, on the other hand, a multi-step reconfiguration process may be initiated which attempts to minimize the effects of each reconfiguration on the overall performance of the FPGA. In an alternate embodiment, the entire FPGA may be configured as one or more self-testing areas during off-line testing, such as manufacturing testing.

Abstract translation: 现场可编程门阵列（FPGA）的容错操作方法，无论作为片上系统或其他专用集成电路的嵌入式部分，在正常在线操作过程中利用增量重新配置，包括将FPGA配置为自身 测试区和工作区。 在自检区域内，可以对FPGA的可编程互连资源进行故障测试。 在检测到互连资源内的一个或多个故障时，识别故障的互连资源，并确定故障互连资源的利用是否与FPGA的预期操作兼容。 如果故障的互连资源与FPGA的预期操作兼容，则可以利用故障互连资源来提供FPGA的容错操作。 如果故障的互连资源与FPGA的预期操作不兼容，另一方面，可以启动多步骤重新配置过程，其尝试最小化每个重配置对FPGA总体性能的影响。 在替代实施例中，整个FPGA可以被配置为离线测试期间的一个或多个自检区域，例如制造测试。

公开(公告)号：US12001288B2

公开(公告)日：2024-06-04

申请号：US17484310

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Kiran Kumar Malipeddi ,  Shekar Babu Merla ,  Pranav Agrawal

IPC: G06F11/00 ,  G06F11/14 ,  G06F13/16 ,  G11C29/38

CPC classification number: G06F11/1428 ,  G06F11/1417 ,  G06F13/1668 ,  G11C29/38

Abstract: Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

公开(公告)号：US11977447B2

公开(公告)日：2024-05-07

申请号：US17742164

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Sik Choi ,  Yun-Ho Youm ,  Jae Sung Yoo

IPC: G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1428 ,  G06F2201/805

Abstract: A storage device with improved security performance is provided. The storage device comprises a first non-volatile memory storing a firmware image, a second non-volatile memory storing an emergency image, and a storage controller controlling the first and second non-volatile memories, wherein the storage controller checks an integrity of the firmware image received from the first non-volatile memory, loads and executes the emergency image from the second non-volatile memory when the integrity check of the firmware image fails, receives a recover image from an external device based on the emergency image, and provides the recover image to the first non-volatile memory.

公开(公告)号：US11892909B2

公开(公告)日：2024-02-06

申请号：US17207424

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F11/00 ,  G06F11/14 ,  G06F3/06

CPC classification number: G06F11/1428 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2201/85

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of at least one memory device of the set, wherein the failure affects stored data; notifying a host system of a change in a capacity of the set of memory devices; receiving from the host system an indication to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.

公开(公告)号：US20170168984A1

公开(公告)日：2017-06-15

申请号：US15061045

申请日：2016-03-04

Applicant: International Business Machines Corporation

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Matthew S. Doyle ,  Mark J. Jeanson ,  Mark O. Maxson

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F11/1428 ,  G06F13/4018 ,  G06F13/4068 ,  G06F13/4282

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

公开(公告)号：US20170168983A1

公开(公告)日：2017-06-15

申请号：US14968166

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Matthew S. Doyle ,  Mark J. Jeanson ,  Mark O. Maxson

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F11/1428 ,  G06F13/4018 ,  G06F13/4068 ,  G06F13/4282

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

公开(公告)号：US20170003347A1

公开(公告)日：2017-01-05

申请号：US15113020

申请日：2015-01-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Mohamed BENAZOUZ

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31718 ,  G01R31/31703 ,  G01R31/31704 ,  G01R31/3177 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/1428 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2051

Abstract: A method implemented by computer for compressing and decompressing all the fault scenarios of a processor comprising computation units interconnected by a communication network having topology symmetries, each fault scenario corresponding to the number and the location of one or more failing computation units and the method comprises the steps of reception or determination of one or more topology symmetries; determination of the equivalent scenarios by means of said topology symmetries; each of the fault equivalence classes being associated with a resource allocation solution in terms of mapping and routing. Different developments include the determination or the application of an inference engine, of identifiers associated with the fault scenarios, of combinatorial exploration techniques, of compression rates, of reconfiguration of the processor and of classification of the processor in a range. A program product and associated systems are also described.

Abstract translation: 一种由计算机实现的用于压缩和解压缩处理器的所有故障场景的方法，包括由具有拓扑对称性的通信网络互连的计算单元，与一个或多个故障计算​​单元的数量和位置相对应的每个故障情景以及所述方法包括： 接收或确定一个或多个拓扑对称的步骤; 通过所述拓扑对称来确定等效场景; 在映射和路由方面，每个故障等价类与资源分配解决方案相关联。 不同的发展包括确定或应用推理机，与故障场景相关联的标识符，组合探测技术，压缩率，处理器重新配置以及处理器在一个范围内的分类。 还描述了程序产品和相关系统。

公开(公告)号：US20160380819A1

公开(公告)日：2016-12-29

申请号：US14752778

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger

IPC: H04L12/24

CPC classification number: H04L41/0816 ,  G06F11/00 ,  G06F11/0709 ,  G06F11/0793 ,  G06F11/1428 ,  G06F11/3003

Abstract: Aspects extend to methods, systems, and computer program products for (re)configuring acceleration components over a network. (Re)configuration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During (re)configuration, connectivity can be maintained for any other functionality at the acceleration component untouched by the (re)configuration. Network (re)configuration of acceleration components facilitates management of acceleration components and accelerated services from a centralized service. Network (re)configuration of acceleration components also relieves host components from having to store (potentially diverse and numerous) image files.

Abstract translation: 方面扩展到方法，系统和计算机程序产品，用于（重新）通过网络配置加速组件。 （Re）配置可以由于各种原因而实现，包括解决加速组件的功能错误或更新加速组件的功能。 在（重新）配置期间，可以通过（重新）配置不改变加速组件的任何其他功能来维持连接。 加速组件的网络（重新）配置有助于从集中式服务管理加速组件和加速服务。 加速组件的网络（重新）配置也可以减轻主机组件不必存储（潜在的多种多样）图像文件。