公开(公告)号：US20240267081A1

公开(公告)日：2024-08-08

申请号：US18566241

申请日：2022-12-12

Applicant: LEONARDO S.P.A.

Inventor： Marco D'Ambrosio

IPC: H04B1/7073 ,  H04L12/40

CPC classification number: H04B1/7073 ,  H04L12/40032 ,  H04B2201/7073

Abstract: Communication system, comprising: a first data bus configured to transport a first data signal according to a first transmission direction; a second data bus configured to transport a second data signal according to a second transmission direction different from the first transmission direction; a synchronization bus; and a plurality of local resources generating a respective local signal to be transmitted on the first and second data bus. All transceivers are modulated with CDMA encoding and take place following a synchronism signal. The unidirectionality of transmission on the data buses guarantees the absence of interference. The communication system is fully scalable.

公开(公告)号：US11936391B2

公开(公告)日：2024-03-19

申请号：US17876473

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ruediger Kuhn ,  Maciej Jankowski

IPC: H03L7/099 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/087 ,  H04B2201/7073

Abstract: In some examples, a circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the PFD.

公开(公告)号：US11929777B2

公开(公告)日：2024-03-12

申请号：US17692801

申请日：2022-03-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiaolin Jia

IPC: H04B1/7073 ,  H04B1/69

CPC classification number: H04B1/7073 ,  H04B2001/6908 ,  H04B2201/7073

Abstract: A time synchronization method and apparatus includes determining a time difference between reference time and system time of an artificial intelligence device, where the reference time is timed by an internal clock of the artificial intelligence device and is aligned based on a satellite timing signal, or the reference time is timed by an internal clock of the artificial intelligence device; and adjusting the system time based on a preset step value if the time difference is greater than a preset value.

公开(公告)号：US11855681B2

公开(公告)日：2023-12-26

申请号：US17093372

申请日：2020-11-09

Applicant: GUANGZHOU ON-BRIGHT ELECTRONICS CO., LTD.

Inventor： Jiaqiang Huang ,  Jiapeng Zhang

IPC: H04B1/7073 ,  H04B1/709 ,  H04L27/38

CPC classification number: H04B1/7073 ,  H04B1/709 ,  H04L27/3818 ,  H04B2201/694 ,  H04B2201/7073

Abstract: System and method for processing an analog signal. For example, a demodulator for processing an analog signal includes one or more analog-to-digital converters configured to receive an analog signal and generate a digital signal based at least in part on the analog signal, and a correlator coupled to the one or more analog-to-digital converters and configured to generate a stream of correlation results including a first plurality of correlation results, a second plurality of correlation results, and a third plurality of correlation results. The first plurality of correlation results is different from the second plurality of correlation results by at least one correlation result, and the second plurality of correlation results is different from the third plurality of correlation results by at least another correlation result.

公开(公告)号：US20190028139A1

公开(公告)日：2019-01-24

申请号：US15845355

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H04B1/7097 ,  H04B1/7073 ,  H04L7/04 ,  H04L7/00

CPC classification number: H04B1/7097 ,  H04B1/7073 ,  H04B15/04 ,  H04B2201/7073 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/048

Abstract: An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.

公开(公告)号：US20180241431A1

公开(公告)日：2018-08-23

申请号：US15956428

申请日：2018-04-18

Applicant: BroadNet Invest AG

Inventor： Ianelli Zbigniew

IPC: H04B1/7073 ,  H04L27/20 ,  H04B1/707 ,  H04B1/69

CPC classification number: H04B1/7073 ,  H04B1/707 ,  H04B2001/6908 ,  H04B2201/7073 ,  H04L27/2082

Abstract: A method and a device are described for determining data from a signal spread over at least one frequency base band representing the data. The method for generating a signal has a step of using at least one highly auto-correlated spread code sequence (1C, 2C) associated with the frequency base band for determining a delay with which a modulated portion (1P, 2P) of the data is spread on the signal. The method has further steps of determining said modulated portion from the signal using the delay and the spread code sequence (1C, 2C), of demodulating the modulated portion (1P, 2P) using phase shift keying, and of determining a remainder (1R, 2R) of the data using the delay.

公开(公告)号：US10056937B1

公开(公告)日：2018-08-21

申请号：US15717848

申请日：2017-09-27

Applicant: Rupert Theodore Neff

Inventor： Rupert Theodore Neff

IPC: H04B1/00 ,  H04B1/7073 ,  G06F7/58

CPC classification number: H04B1/70735 ,  G06F7/588 ,  H04B2201/7073 ,  H04J13/0074 ,  H04J13/10

Abstract: Presented is a generator of binary code shift key (CSK) codes pre-saved to memory usable for time synchronous CSK code retrievals with extraction capability for 1 of 16 orthogonal CSK symbol codes under control of a supported communications system. The CSK code generator pre-defines a 1332 root prime number sequence containing 6 unique prime numbers including 221-7s, 222-11s, 221-13s, 223-17s, 222-19s, and 223-23s that receive multiple index shuffles of 1332 indexes. Pairs of 1332 shuffled indexes of prime sequences are then merged and formatted into 100 tier0 100 hex character format codes. Two levels of XORs of hex character format code pairs generate CSK codes that are collected into 10000 code files that are saved to memory. Time-synchronous CSK code retrieval is followed by 1 of 16 CSK orthogonal symbol codes extraction based on new half-byte data values under flow control of the supported communications system.

公开(公告)号：US20180048349A1

公开(公告)日：2018-02-15

申请号：US15588431

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Haitong Sun ,  Naga Bhushan ,  Tingfang Ji

IPC: H04B1/7075 ,  H04J13/00 ,  H04J13/10 ,  H04W72/04 ,  H04L1/00

CPC classification number: H04B1/7075 ,  H04B2201/698 ,  H04B2201/7073 ,  H04J13/0007 ,  H04J13/10 ,  H04J2013/0096 ,  H04L1/0042 ,  H04L1/0057 ,  H04L25/00 ,  H04W72/0466

Abstract: Disclosed are methods and apparatus used in wireless communications. The methods and apparatus establish a codebook for use in sparse code multiple access (SCMA) encoded communications, in particular. The SCMA codebook is configured to set the codebook for at least one layer (i.e., a user) to include a constellation of points having a first grouping of constellation points located at first radial distance from an origin in a complex plane and a second grouping of constellation points located at a second radial distance from the origin. This codebook arrangement provides increased gains at receivers by optimizing the constellation shape to improve the distance between constellation points (i.e., SCMA codebook performance), and in particular more robust performance when encountering amplitude and phase misalignment in uplink (UL) multiple access.

公开(公告)号：US09768827B2

公开(公告)日：2017-09-19

申请号：US15028647

申请日：2014-10-10

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Frederic Hameau ,  Gilles Masson ,  Laurent Ouvry

IPC: H04B1/7115 ,  H04B1/7183 ,  H04B1/7163 ,  H04B1/7075

CPC classification number: H04B1/7183 ,  H04B1/70758 ,  H04B1/7115 ,  H04B1/7163 ,  H04B2201/70707 ,  H04B2201/7073 ,  H04B2201/70979 ,  H04B2201/7163

Abstract: A UWB impulse receiver including an RF stage followed by a baseband processing stage. The baseband processing stage includes a Rake filter including a plurality of time fingers, each finger including an integrator of the baseband signal during an acquisition window, a control module, and a detection module estimating the received symbols from the integration results. During a synchronization phase, the control module drives respective positions of the acquisition windows associated with the different fingers, to scan at a reception interval, the RF stage only operating, in a course of the synchronization phase, during the plurality of acquisition windows.

公开(公告)号：US09584177B2

公开(公告)日：2017-02-28

申请号：US15041217

申请日：2016-02-11

Applicant: NXP B.V.

Inventor： Nenad Pavlovic ,  Vladislav Dyachenko ,  Tarik Saric

IPC: H04L1/00 ,  H04B1/7073 ,  H03L7/197 ,  H04B1/69 ,  H03C3/09

CPC classification number: H04B1/7073 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03L7/1976 ,  H04B2001/6912 ,  H04B2201/7073

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.

Abstract translation: 公开了一种具有频率控制振荡器，反馈路径，时间到数字转换器和存储器的锁相环。 频率控制振荡器包括用于改变频率控制振荡器的输出频率以跟踪参考频率的第一控制输入和用于调制输出信号的频率以产生啁啾的第二控制输入。 反馈路径被配置为向时间到数字转换器提供输入信号，并且包括调制解除模块，其可操作以从输出信号中去除由第二控制输入产生的频率调制。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入的响应中的非线性的第二控制输入值。 锁相环可以在啁啾模式下操作，其中通过基于存储器中存储的第二控制输入值确定与期望啁啾频率对应的第二控制输入的值来产生第二控制输入，其中， 锁相环被配置为基于调制消除模块从其中移除由第二控制输入产生的频率调制的反馈路径来确定第一控制输入。