公开(公告)号：US20190026232A1

公开(公告)日：2019-01-24

申请号：US15655182

申请日：2017-07-20

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Cyprien LAPLACE ,  Ye LI ,  Regis DUCHESNE

IPC: G06F12/1036 ,  H04L12/801 ,  H04L12/755 ,  H04L12/24

Abstract: An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.

公开(公告)号：US20190018789A1

公开(公告)日：2019-01-17

申请号：US15650056

申请日：2017-07-14

Applicant: ARM LTD

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F12/1027 ,  G06F11/07 ,  G06F9/32 ,  G06F9/34 ,  G06F12/1036 ,  G06F9/38

Abstract: Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space; detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store; in which the detector circuitry is configured, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, to retrieve one or more further instances of the translation data; and translation circuitry to apply the translation defined by a detected instance of the translation data to the given virtual memory address.

公开(公告)号：US10169246B2

公开(公告)日：2019-01-01

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1036

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：US10169091B2

公开(公告)日：2019-01-01

申请号：US13660799

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F9/46 ,  G06F15/173 ,  G06F9/50 ,  G06F12/1045 ,  G06F9/48 ,  G06F9/455 ,  G06F12/109 ,  G06F12/1036

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US20180373644A1

公开(公告)日：2018-12-27

申请号：US15633388

申请日：2017-06-26

Applicant: Western Digital Technologies, Inc.

Inventor： Daniel Joseph Linnen ,  Ashish Ghai ,  Dongxiang Liao ,  Srikar Peesari ,  Avinash Rajagiri ,  Philip Reusswig ,  Bin Wu

IPC: G06F12/1036 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F12/10

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

公开(公告)号：US10162745B2

公开(公告)日：2018-12-25

申请号：US15234431

申请日：2016-08-11

Applicant: AO Kaspersky Lab

Inventor： Vladislav V. Pintiysky ,  Denis V. Anikin ,  Dmitry A. Kirsanov

IPC: G06F9/50 ,  G06F12/02 ,  G06F12/08 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1036

Abstract: Disclosed are system and method for controlling execution of a program. An example method includes determining a memory sector for storing at least a portion of execution instructions of the computer program in virtual memory address space; determining, in the virtual memory address space, one or more pages that contain code instructions and data associated with the memory sector; creating a duplicate of the virtual memory address space comprising the memory sector and the one or more pages; tagging the memory sector and the one or more pages in both the virtual memory address space and its duplicate; receiving a notification to transfer execution of the computer program between different memory sectors while executing instructions stored in either the virtual memory address space or its duplicate; and transferring execution of the computer program to a memory location other than the one in which the notification was received.

公开(公告)号：US10162659B2

公开(公告)日：2018-12-25

申请号：US14953909

申请日：2015-11-30

Applicant: ARM Finance Overseas Limited

Inventor： Sanjay Patel ,  Ranjit Joseph Rozario

IPC: G06F12/10 ,  G06F12/14 ,  G06F9/455 ,  G06F12/1036 ,  G06F12/109

Abstract: A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.

公开(公告)号：US20180336140A1

公开(公告)日：2018-11-22

申请号：US15981402

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： VISHAK GUDDEKOPPA ,  ARUN GEORGE ,  MUTHA SANJAY MITESH ,  RAKESH NADIG

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/02 ,  G06F12/126

Abstract: A method for flash-aware heap memory management includes reserving a contiguous virtual space in a memory space of at least one process with a size equivalent to a size of a flash-based byte addressable device. The method also includes partitioning by a host device the memory space of the flash-based byte addressable device into multiple chunks. Each chunk includes multiple logical segments. The host device receives a memory allocation request from a thread associated with an application. The host device determines at least one chunk from the multiple chunks, including a least free logical segment compared to the other chunks from the multiple chunks. The host device allocates to the thread at least one chunk that includes the least free logical segment.

公开(公告)号：US10120813B2

公开(公告)日：2018-11-06

申请号：US15452989

申请日：2017-03-08

Applicant: ARM Limited

Inventor： John Michael Horley ,  Dan Brook

IPC: G06F12/1009 ,  G06F12/1036

Abstract: Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.

公开(公告)号：US20180285375A1

公开(公告)日：2018-10-04

申请号：US15666606

申请日：2017-08-02

Applicant: VMWARE, INC.

Inventor： ASIT DESAI ,  BRYAN BRANSTETTER ,  PRASANNA AlTHAL ,  PRASAD RAO JANGAM ,  MAHESH S. HIREGOUDAR ,  ROHAN PASALKAR

IPC: G06F17/30 ,  G06F12/02 ,  G06F12/1036

CPC classification number: G06F16/13 ,  G06F12/023 ,  G06F12/1036 ,  G06F16/1727 ,  G06F2212/1044 ,  G06F2212/65

Abstract: Exemplary methods, apparatuses, and systems determine whether a skip optimization process can be used to store a file in a storage space. When it is determined that the skip optimization can be performed, a file stored in the storage space can be referenced in a file metadata data structure using direct addressing of file blocks storing the file instead of through indirect addressing (e.g., pointer addresses stored in pointer blocks).