公开(公告)号：US20190018790A1

公开(公告)日：2019-01-17

申请号：US15649930

申请日：2017-07-14

Applicant: ARM LTD

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F12/1036 ,  G06F12/1045 ,  G06F12/1081

CPC classification number: G06F12/1036 ,  G06F12/1054 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/656 ,  G06F2212/657

Abstract: A system, apparatus and method are provided in which a range of virtual memory addresses and a copy of that range are mapped to the same first system address range in a data processing system until an address in the virtual memory address range, or its copy, is written to. The common system address range includes a number of divisions. Responsive to a write request to an address in a division of the common address range, a second system address range is generated. The second system address range is mapped to the same physical addresses as the first system address range, except that the division containing the address to be written to and its corresponding division in the second system address range are mapped to different physical addresses. First layer mapping data may be stored in a range table buffer and updated when the second system address range is generated.

公开(公告)号：US20190018808A1

公开(公告)日：2019-01-17

申请号：US15650008

申请日：2017-07-14

Applicant: ARM LTD

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F13/16 ,  H04L12/947 ,  H04L12/931

CPC classification number: G06F13/1694 ,  G06F12/0824 ,  G06F12/0826 ,  G06F12/1036 ,  G06F12/1072 ,  G06F12/1081 ,  G06F13/1663 ,  G06F2212/2542 ,  G06F2212/651 ,  G06F2212/657 ,  H04L49/252 ,  H04L49/35 ,  H04L49/505

Abstract: A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

公开(公告)号：US20190018789A1

公开(公告)日：2019-01-17

申请号：US15650056

申请日：2017-07-14

Applicant: ARM LTD

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F12/1027 ,  G06F11/07 ,  G06F9/32 ,  G06F9/34 ,  G06F12/1036 ,  G06F9/38

Abstract: Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space; detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store; in which the detector circuitry is configured, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, to retrieve one or more further instances of the translation data; and translation circuitry to apply the translation defined by a detected instance of the translation data to the given virtual memory address.

公开(公告)号：US20190018794A1

公开(公告)日：2019-01-17

申请号：US15649976

申请日：2017-07-14

Applicant: ARM LTD

Inventor： Jonathan Curtis BEARD ,  Roxana RUSITORU ,  Curtis Glenn DUNHAM

IPC: G06F12/1045 ,  G06F9/50 ,  G06F12/0864 ,  G06F12/1009 ,  G06F9/48

CPC classification number: G06F12/1063 ,  G06F9/30123 ,  G06F9/461 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0864 ,  G06F12/1009 ,  G06F2212/6032 ,  G06F2212/6046 ,  G06F2212/657

Abstract: A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.

公开(公告)号：US20180293169A1

公开(公告)日：2018-10-11

申请号：US15483036

申请日：2017-04-10

Applicant: ARM Ltd

Inventor： Jonathan Curtis BEARD ,  Peter VAN HENSBERGEN

IPC: G06F12/0831 ,  G06F12/1045 ,  G06F12/0875 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F11/1064 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0875 ,  G06F12/1054 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

Abstract: A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.