公开(公告)号：US20130168801A1

公开(公告)日：2013-07-04

申请号：US13421996

申请日：2012-03-16

Applicant: TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

Inventor： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

Abstract translation: 本公开涉及形成隔离区域的方法。 该方法包括以下步骤：提供具有第一类型的离子掺杂剂的衬底，其中衬底具有形成在单元区域上的多个沟槽和衬底的单元区域之间的隔离区域与沟槽的侧壁 其上形成有氧化层，并且沟槽填充有金属结构; 从隔离区的沟槽移除金属结构; 在隔离区的沟槽下方将第二类型的离子注入到衬底中; 并用绝缘结构填充所有沟槽，其中隔离区域的沟槽由绝缘结构完全填充以形成非金属隔离区域。

公开(公告)号：US20130140620A1

公开(公告)日：2013-06-06

申请号：US13398853

申请日：2012-02-17

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L27/11524

Abstract: The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same.

Abstract translation: 本发明公开了一种闪速存储器。 闪速存储器包括依次设置在基板上的基板和存储器串，多个着陆焊盘，多个公共源极线，多个位线触点和至少一个位线。 该存储器串包括多个存储晶体管。 着陆焊盘设置在每个存储晶体管之间。 公共源线和位线接触件可替换地电连接到着陆焊盘。 公共线设置在公共线路触点上并与其电连接。 本发明还提供制造该方法的制造方法。

公开(公告)号：US08455363B2

公开(公告)日：2013-06-04

申请号：US13282593

申请日：2011-10-27

Applicant: Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

Abstract: A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Abstract translation: 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US20130026554A1

公开(公告)日：2013-01-31

申请号：US13196037

申请日：2011-08-02

Applicant: TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

Inventor： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L27/11521

Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate.

Abstract translation: 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元彼此相邻并形成在第一介电层上。 每个数据存储单元包括形成在第一介电层上的至少两个浮动栅极，形成在第一介电层上和两个浮置栅极之间的第二介电层，形成在两个浮置栅极和第二电介质层上的栅极间电介质层 形成在所述栅极间电介质层上的至少一个控制栅极以及形成在所述第一电介质层上并且与所述两个浮置栅极，所述栅极间介电层和所述控制栅极包围并紧密连接的第三电介质层。

公开(公告)号：US08298892B1

公开(公告)日：2012-10-30

申请号：US13241295

申请日：2011-09-23

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L29/4236

Abstract: A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.

Abstract translation: 一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。 制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。 第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。 第一个沟槽有第一个深度。 然后，去除第一掩埋结构的第一栅极。 之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。 最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

公开(公告)号：US08148766B2

公开(公告)日：2012-04-03

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20120012907A1

公开(公告)日：2012-01-19

申请号：US12874232

申请日：2010-09-02

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L27/108

CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US20120012905A1

公开(公告)日：2012-01-19

申请号：US12899721

申请日：2010-10-07

Applicant: TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

Inventor： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L21/76224 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

Abstract: A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

Abstract translation: 公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。 硅化物衬底具有两个掺杂区域。 氮化物层沉积在硅化物衬底上。 硅化物衬底和氮化物层具有贯穿的凹槽。 两个掺杂区位于凹槽的两侧。 凹部的端部具有比凹部大的蚀刻空间。 硅化物衬底的顶部具有鳍状结构。 两个STI位于硅化物衬底（凹槽）的两个相对侧。 应变氮化物在凹槽​​中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。 两个掺杂区域覆盖了应变氮化物。 结果，提高了半导体的效率，并且提高了驱动电流。

公开(公告)号：US07972924B2

公开(公告)日：2011-07-05

申请号：US12839387

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US20110092044A1

公开(公告)日：2011-04-21

申请号：US12699399

申请日：2010-02-03

Applicant: SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

Inventor： SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC: H01L21/02

CPC classification number: H01L28/92

Abstract: A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.

Abstract translation: 制造电容器下电极的方法包括电介质层，第一氮化硅层和硬掩模层; 部分地蚀刻硬掩模层，第一氮化硅层和电介质层以形成多个凹部; 在所述硬掩模层上沉积第二氮化硅层并进入所述凹部; 部分蚀刻第二氮化硅层，硬掩模层和电介质层以形成多个沟槽; 在每个沟槽内形成电容器下电极，并部分地蚀刻第一氮化硅层，第二氮化硅层，电介质层和电容器下电极以形成蚀刻区域; 并且从蚀刻区域蚀刻除去电介质层，由此每个电容器下电极的周围被第二氮化硅层包围并附着。