公开(公告)号：US12089396B2

公开(公告)日：2024-09-10

申请号：US17724344

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Lee

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H10B12/315 ,  H01L28/92 ,  H10B12/50 ,  H10B12/0335 ,  H10B12/09

Abstract: A semiconductor device may include a cell capacitor including first lower electrodes, a first upper support layer pattern, a first dielectric layer, and a first upper electrode. The decoupling capacitor may include second lower electrodes, a second upper support layer pattern, a second dielectric layer, and a second upper electrode. The first and second lower electrodes may be arranged in a honeycomb pattern at each vertex of a hexagon and a center of the hexagon. The first upper support layer pattern may be connected to upper sidewalls of the first lower electrodes. The first upper support layer pattern may correspond to a first plate defining first openings. The second upper support layer pattern may be connected to upper sidewalls of the second electrodes. The second upper support layer pattern may correspond to a second plate defining second openings having a shape different from a shape of the first opening.

公开(公告)号：US12087684B2

公开(公告)日：2024-09-10

申请号：US17751699

申请日：2022-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Yi Chen ,  Yung-Chow Peng ,  Chung-Chieh Yang

IPC: H01L23/522 ,  H01L23/552 ,  H01L49/02 ,  H03M1/38

CPC classification number: H01L23/5225 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/552 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/92 ,  H03M1/38

Abstract: An integrated circuit structure includes a first capacitor structure, disposed in a first layer on a semiconductor substrate and comprising a plurality of capacitors; a second capacitor structure, adjacent to first capacitor structure in the first layer, wherein the second capacitor structure and the first capacitor structure are arranged as a strip-shaped structure; a first conductive plate, disposed at one end of the strip-shaped structure in the first layer; and a second conductive plate, disposed in a second layer on the semiconductor substrate over the strip-shaped structure and extending toward the other end of the strip-shaped structure from the one end of the strip-shaped structure.

公开(公告)号：US12080755B2

公开(公告)日：2024-09-03

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/495 ,  H01L27/08 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US12048138B2

公开(公告)日：2024-07-23

申请号：US17502324

申请日：2021-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangshu Zhan ,  Qiang Wan ,  Penghui Xu ,  Tao Liu ,  Sen Li ,  Jun Xia

IPC: H10B12/00 ,  H01L49/02

CPC classification number: H10B12/03 ,  H01L28/91 ,  H01L28/92 ,  H10B12/033 ,  H10B12/0335

Abstract: The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.

公开(公告)号：US20240234490A1

公开(公告)日：2024-07-11

申请号：US18611843

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L28/92 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223

Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

公开(公告)号：US12034039B2

公开(公告)日：2024-07-09

申请号：US17451172

申请日：2021-10-18

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： EeJan Khor ,  Ramasamy Chockalingam ,  Juan Boon Tan

IPC: H01L49/02

CPC classification number: H01L28/92

Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

公开(公告)号：US20240222422A1

公开(公告)日：2024-07-04

申请号：US18092162

申请日：2022-12-30

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Christopher J. Penny

IPC: H01L21/02

CPC classification number: H01L28/92

Abstract: A multi-stack metal-insulator-metal (MIM) structure includes a plurality of conductive plates including a first group comprising odd-numbered ones of the plates and a second group comprising even-numbered ones of the plates. All of the conductive plates are of an identical material. A plurality of insulators are between the plurality of conductive plates; and a first plate via contact extends vertically through the plurality of conductive plates and the plurality of insulators. The first plate via contact is electrically coupled to the first group of conductive plates and electrically isolated from the second group of conductive plates. The second plate via contact extends vertically through the plurality of conductive plates and the plurality of insulators. The second plate via contact is electrically coupled to the second group of conductive plates and electrically isolated from the first group of conductive plates.

公开(公告)号：US11996440B2

公开(公告)日：2024-05-28

申请号：US17455777

申请日：2021-11-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Xiaoyu Yang ,  Liang Zhao

IPC: H01L23/52 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/92 ,  H01L28/91 ,  H10B12/03 ,  H10B12/30

Abstract: The present disclosure provides a method for manufacturing capacitor array, including: forming, on an upper surface of the substrate, a laminated structure including sacrificial layers and support layers; forming a patterned mask layer on an upper surface of the laminated structure; etching the laminated structure based on the patterned mask layer to form a through hole, wherein after the through hole is formed, the patterned mask layer is retained on the upper surface of the laminated structure, and the through hole penetrates through the patterned mask layer and the laminated structure; forming a first electrode on a sidewall and at a bottom of the through hole; forming, in the patterned mask layer and the laminated structure, and removing the sacrificial layer based on the opening; forming a capacitor dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the capacitor dielectric layer.

公开(公告)号：US11996438B1

公开(公告)日：2024-05-28

申请号：US17552345

申请日：2021-12-15

Applicant: Kepler Computing Inc.

Inventor： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC: G11C11/22 ,  H01L49/02 ,  H10B51/30 ,  H10B53/30

CPC classification number: H01L28/57 ,  G11C11/221 ,  H01L28/91 ,  H01L28/92 ,  H10B51/30 ,  H10B53/30

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US11961881B2

公开(公告)日：2024-04-16

申请号：US17445993

申请日：2021-08-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Lingxiang Wang

IPC: H10B12/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92 ,  H10B12/00

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being included between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.