公开(公告)号：US20170358462A1

公开(公告)日：2017-12-14

申请号：US15621493

申请日：2017-06-13

Applicant: J-DEVICES CORPORATION

Inventor： Seita ARAKI ,  Kazuhiko KITANO

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/83

Abstract: A manufacturing method of a semiconductor package includes disposing one or more semiconductor devices on a base substrate, each of the one or more semiconductor devices having an external terminal; forming a frame on the base substrate, the frame surrounding the one or more semiconductor devices; and forming a resin insulating layer inside the frame, the resin insulating layer sealing the one or more semiconductor devices and the resin insulating layer including a resin insulating material; wherein a surface of each of the one or more semiconductor devices on which the external terminal is not provided faces the base substrate.

公开(公告)号：US20170338136A1

公开(公告)日：2017-11-23

申请号：US15600082

申请日：2017-05-19

Applicant: J-DEVICES CORPORATION

Inventor： Minoru KAI

IPC: H01L21/67 ,  H01L23/498 ,  H01L21/68 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L21/67132 ,  H01L21/67144 ,  H01L21/681 ,  H01L21/6838 ,  H01L23/147 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/75

Abstract: A semiconductor manufacturing apparatus includes a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips; a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator; a pickup unit picking up each of the plurality of semiconductor chips; and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit; wherein the pickup unit moves the semiconductor chip from the stage to a mounting position of a supporting substrate and adherers the semiconductor chip by the control unit.

公开(公告)号：US20170317045A1

公开(公告)日：2017-11-02

申请号：US15481848

申请日：2017-04-07

Applicant: J-DEVICES CORPORATION

Inventor： Toshiyuki INAOKA ,  Atsuhiro URATSUJI

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L24/04 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/64 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/03001 ,  H01L2224/03618 ,  H01L2224/03632 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2224/83

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.

公开(公告)号：US20170316996A1

公开(公告)日：2017-11-02

申请号：US15472387

申请日：2017-03-29

Applicant: J-DEVICES CORPORATION

Inventor： Yasuyuki TAKEHARA ,  Kazuhiko KITANO

IPC: H01L23/29 ,  H01L21/306 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

公开(公告)号：US20170263537A1

公开(公告)日：2017-09-14

申请号：US15446426

申请日：2017-03-01

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US09627289B2

公开(公告)日：2017-04-18

申请号：US14964121

申请日：2015-12-09

Applicant: J-Devices Corporation

Inventor： Yoshihiko Ikemoto ,  Shigenori Sawachi ,  Fumihiko Taniguchi ,  Akio Katsumata

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/552 ,  H01L23/498

CPC classification number: H01L23/3142 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267

Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.

公开(公告)号：US09601450B2

公开(公告)日：2017-03-21

申请号：US14669491

申请日：2015-03-26

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu Hosoyamada ,  Yoshikazu Kumagaya ,  Tomoshige Chikai ,  Shingo Nakamura ,  Hiroaki Matsubara ,  Shotaro Sakumoto

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/36 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

公开(公告)号：US20160351511A1

公开(公告)日：2016-12-01

申请号：US15235439

申请日：2016-08-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yasuyuki TAKEHARA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

公开(公告)号：US20160233141A1

公开(公告)日：2016-08-11

申请号：US15018563

申请日：2016-02-08

Applicant: J-DEVICES CORPORATION

Inventor： Masao HIROBE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3736 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13101 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/059 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/16153 ,  H01L2924/1616 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0655 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/0635 ,  H01L2924/0675 ,  H01L2924/00

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

Abstract translation: 提供了一种半导体器件，其包括其表面由绝缘材料制成的衬底，连接在衬底上的半导体芯片倒装芯片和经由热界面材料接合到半导体芯片的散热器，并且固定到衬底外部的衬底 半导体芯片，其中散热器具有突出部分，突出部分朝向基板突出并且通过导电树脂在接合到半导体芯片的部件和固定到基板的部件之间并且散热器接合到基板上，具有应力吸收部分。 根据本发明，防止散热器的突起部在散热片的突出部分接合到基板的部分处从基板剥离。

公开(公告)号：US20160225701A1

公开(公告)日：2016-08-04

申请号：US15010988

申请日：2016-01-29

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiro TANAKA

IPC: H01L23/495

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract translation: 根据本发明的一个实施例的半导体器件包括半导体元件，具有使用第一金属固定半导体元件的表面的岛和由第二金属形成的第一图案，第一图案被布置在一个上 表面的一部分，其中当第一金属熔化时，第二金属具有比表面更大的润湿特性。