公开(公告)号：US20060101172A1

公开(公告)日：2006-05-11

申请号：US11320277

申请日：2005-12-27

Applicant: Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

IPC: G06F5/00

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract translation: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US06996650B2

公开(公告)日：2006-02-07

申请号：US10147682

申请日：2002-05-16

Applicant: Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

Inventor： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/40

CPC classification number: G06F13/4273 ,  G06F13/4059

Abstract: A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Abstract translation: 提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。 多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。 每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。 发送缓冲区提供发送源和串行器之间的异步接口。 串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。 发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。 发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

公开(公告)号：US20050232270A1

公开(公告)日：2005-10-20

申请号：US11152699

申请日：2005-06-14

Applicant: Brian Bass ,  Jean Calvignac ,  Anthony Gallo ,  Marco Heddes ,  Sridhar Rao ,  Michael Siegel ,  Brian Youngman ,  Fabrice Verplanken

Inventor： Brian Bass ,  Jean Calvignac ,  Anthony Gallo ,  Marco Heddes ,  Sridhar Rao ,  Michael Siegel ,  Brian Youngman ,  Fabrice Verplanken

IPC: G06F15/16 ,  G06F13/40 ,  G06F15/177 ,  H04L12/56

CPC classification number: H04L49/3036 ,  G06F13/4022 ,  H04L49/15 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：US20050177644A1

公开(公告)日：2005-08-11

申请号：US10772737

申请日：2004-02-05

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC: G06F15/16 ,  H04L12/56

CPC classification number: H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

Abstract translation: 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

公开(公告)号：US06370148B1

公开(公告)日：2002-04-09

申请号：US09110920

申请日：1998-07-06

Applicant: Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Gilles Toubol

Inventor： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Gilles Toubol

IPC: H04J314

CPC classification number: H04L49/106 ,  H04L49/20 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/508

Abstract: An improved arbiter is described for arbitrating requests by a plurality of first data processing units for access to a plurality of second data processing units interconnected by a switching system of a type in which at any time each first unit can only access one second unit and each second unit can only be accessed by one first unit. The arbiter comprises a scheduler mechanism for repeatedly selecting access requests with a defined minimum probability of selecting a request for each first unit-second unit combination. Rearrangement storage means records requests selected by the scheduler mechanism. A rearranger is provided for repeatedly selecting a set of requests recorded in the rearrangement storage means, so that only one request per first unit and per second unit is selected, using a priority mechanism which increases the probability of selection with the length of time a request is stored in the rearrangement storage means. Finally, means are provided for communicating the grant of the selected set of requests to the switching system and for deleting the selected set of requests from the rearrangement storage means. In one embodiment, the arbiter is used for controlling switching paths in a packet data switch.

Abstract translation: 描述了一种改进的仲裁器，用于对多个第一数据处理单元的请求进行仲裁，以访问多个第二数据处理单元，该多个第二数据处理单元通过一种类型的交换系统互连，其中每个第一单元在任何时候只能访问一个第二单元，并且每个 第二单元只能由一个第一单元访问。 仲裁器包括一个调度机制，用于以对每个第一单位 - 第二单位组合选择一个请求的限定的最小概率重复地选择访问请求。 重排存储装置记录由调度机制选择的请求。 提供了一种重排器，用于重复选择记录在重排存储装置中的一组请求，使得仅使用优先级机制选择每第一单元和每秒单元的一个请求，该优先级机制随着请求的长度增加选择的概率 存储在重排存储装置中。 最后，提供了用于将所选择的一组请求的许可传送给交换系统并且用于从重排存储装置中删除所选择的一组请求的装置。 在一个实施例中，仲裁器用于控制分组数据交换机中的交换路径。

公开(公告)号：US5787071A

公开(公告)日：1998-07-28

申请号：US554113

申请日：1995-11-06

Applicant: Claude Basso ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04

CPC classification number: H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/563 ,  H04L2012/5632 ,  H04L2012/5635 ,  H04L2012/5636 ,  H04L2012/5651 ,  H04L2012/5652

Abstract: A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.

Abstract translation: 通信系统包括通过包括多个连接的链路互连的多个节点。 节点之间的流量由保留的带宽服务和/或非保留带宽服务建立。 非保留带宽服务由逐跳背压机制控制。 当进入节点的流量超过高阈值时，背压机制产生停止背压原语，以节流输入流量。 在拥塞的情况下，该机制能够选择性地插入有助于拥塞的连接而不影响链路业务的其余部分，或全局地停止所有链路业务。 如果流量低于低阈值，流量可以恢复。

公开(公告)号：US5687356A

公开(公告)日：1997-11-11

申请号：US579555

申请日：1995-12-27

Applicant: Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Fabrice Verplanken

IPC: G06F13/00 ,  H04L7/00 ,  H04L12/433 ,  H04L12/64 ,  G06F9/00

CPC classification number: H04L12/6418 ,  H04L12/433 ,  H04L2012/6437 ,  H04L2012/6451 ,  H04L2012/6454 ,  H04L2012/6459

Abstract: A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46). The switch and other concentration logic receive a hub local clock (412). Isochronous traffic interchanges with the hub backplane through leads 410 and 411; between ports or between ports and the hub through leads 407 and 409. Data to a connected station is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

Abstract translation: 具有用于将站附接到LAN的端口的集线器包括用于处理复用的进入和输出令牌环和等时信号流的集中逻辑（14）。 浓度逻辑包括来自输入令牌环分组数据流（40）的时钟恢复逻辑（42），用于在输出（400）上再生差分曼彻斯特编码数据，以及恢复令牌环时钟（401）。 周期成帧发生器（43）从集线器背板（402）和令牌环时钟（401）接收125 us同步时钟，并产生到10个端口中的每一个的控制信号（403）。 每个端口由端口传输接口（44）和端口接收接口（45）组成。 来自连接站的数据被输入（404）到端口接收接口（45）。 令牌环包差分曼彻斯特编码数据输出（406）到下一个有效端口，特别是与其恢复的选通时钟（405）一起输出到其端口传输接口，同时将ISO数据输出（407）转换为开关（46）。 交换机和其他集中逻辑接收集线器本地时钟（412）。 通过引线410和411与轮毂底板进行同步通信交换; 通过引线407和409在端口之间或端口之间以及集线器之间。从端口传输接口（44）输出到连接站的数据（408）。 接收差分曼彻斯特编码数据（400）以及令牌环时钟（401）。 控制信号被输入（403）。 接收同步数据（409）。 令牌环包差分曼彻斯特编码数据最终从浓度逻辑输出（41）。

公开(公告)号：US5668798A

公开(公告)日：1997-09-16

申请号：US547827

申请日：1995-10-25

Applicant: Gilles Toubol ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Luc Torres ,  Fabrice Verplanken

Inventor： Gilles Toubol ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Luc Torres ,  Fabrice Verplanken

IPC: H04L12/70 ,  H04Q11/04 ,  H04L12/56

CPC classification number: H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5616

Abstract: A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.

Abstract translation: 诸如ATM或异步传输模式开关的数据交换设备包括具有多个输入和输出引线的交换结构。 该设备还包括至少一个用于在多个输入端口中的每一个上接收数据单元的输入适配器和至少一个输出适配器，用于将通过交换结构交换的数据单元传送到一组输出端口中的目标端口。 在进入的单元格上执行错误和格式检查，并且保留在特定输入端口上接收到的良好单元和无效单元的数量的计数。 为了降低硬件成本，将计数保存在随机存取存储器中，该存储器在输入端口之间共享。 将几个存储位置分配给每个输入端口以维持必要的计数。

公开(公告)号：US5666361A

公开(公告)日：1997-09-09

申请号：US547826

申请日：1995-10-25

Applicant: Ange Aznar ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Dominique Rigal ,  Luc Torres ,  Fabrice Verplanken

Inventor： Ange Aznar ,  Jean Calvignac ,  Jean-Luc Frenoy ,  Daniel Orsatti ,  Dominique Rigal ,  Luc Torres ,  Fabrice Verplanken

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/935 ,  H04L12/937 ,  H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/255 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5681

Abstract: The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

Abstract translation: 通过执行两次查找操作来增强在输入适配器和输出适配器之间切换ATM信元所需的技术。 在接收要切换的单元的输入适配器中执行第一查找操作。 第一个查找操作检索目标输出端口的地址和连接控制块。 第二个查找操作在目标输出适配器中执行，并利用输入适配器搜索的结果来检索需要完成将单元传输到目标输出端口的信息。

公开(公告)号：US5629928A

公开(公告)日：1997-05-13

申请号：US570840

申请日：1995-12-12

Applicant: Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

Inventor： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

IPC: H04Q3/00 ,  H04L12/56

CPC classification number: H04L12/5602 ,  H04L47/10 ,  H04L49/3081 ,  H04L2012/5619 ,  H04L2012/5635 ,  H04L2012/5679

Abstract: A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.

Abstract translation: 一种在虚拟路径ATM通信系统中实现的流控制装置，包括由包括多个虚拟信道的虚拟路径的物理链路互连的多个节点。 两个节点之间的连接被定义为物理链路，虚拟路径和虚拟信道的组合。 连接在保留的带宽服务和尽力而为的服务之间共享。 通过分析其虚拟连接标识符，在所述尽力服务上传送的ATM数据单元从节点路由到节点。 根据需要从空闲队列池分配的队列用于存储具有相同虚拟信道标识符的所有传入ATM数据单元。