公开(公告)号：US20040119723A1

公开(公告)日：2004-06-24

申请号：US10454506

申请日：2003-06-05

Applicant: Renesas Technology Corp.

Inventor： Yoshitsugu Inoue ,  Akira Torii

IPC: G09G005/00

CPC classification number: G06T11/60 ,  G06T15/10

Abstract: An apparatus for manipulating a face image such as a portrait which produces visual effects to keep interesting a user with simple processes without requiring preparation of a complex model and a number-crunching process for processing the model is provided. Boundary determining means (111) determines a boundary used for bending a face image in a vertical direction of a face image. Image manipulating means (116) bends the face image based on the boundary as determined, to make the face image convex or concave locally around the boundary. Thereafter, the image manipulating means (116) rotates the face image about a rotation axis defined so as to extend in a horizontal direction of the face image, and thereafter projects the face image onto a plane. With those procedures, an expression of a face of the face image can be varied.

Abstract translation: 提供了一种用于操纵诸如肖像的面部图像的装置，其产生视觉效果以使用户简单的过程而不需要准备复杂的模型和用于处理该模型的数字处理过程。 边界确定装置（111）确定用于在面部图像的垂直方向上弯曲脸部图像的边界。 图像处理装置（116）基于所确定的边界弯曲面部图像，以使面部图像在边界周围局部地凸起或凹入。 此后，图像处理装置（116）围绕围绕面部图像的水平方向限定的旋转轴旋转面部图像，然后将面部图像投影到平面上。 通过这些程序，可以改变脸部图像的脸部表情。

公开(公告)号：US20040113904A1

公开(公告)日：2004-06-17

申请号：US10716459

申请日：2003-11-20

Applicant: Renesas Technology Corp.

Inventor： Atsushi Nakamura ,  Kenichiro Omura

IPC: G09G005/00

CPC classification number: G09G5/363 ,  G09G5/397 ,  G09G2320/0247 ,  G09G2340/02

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of null1null, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract translation: 为能够叠加显示的多个显示平面中的每一个分配多页的图像数据存储区域，并且在为每个显示平面执行图像数据存储区域之间切换的同时执行显示输出处理。 在这种显示系统中，能够在不大量加载中央处理单元的情况下启用图像数据存储区域之间的通用切换。 指示终止一个显示平面的TRAP命令的属性位被提供有指示是否在每个显示平面的图像数据存储区域之间进行切换的显示切换使能位。 对于与“1”的显示切换使能位相对应的显示平面，切换到与下一个垂直同步信号同步的定时从其读取图像数据的图像数据存储区域。

公开(公告)号：US20040111592A1

公开(公告)日：2004-06-10

申请号：US10445831

申请日：2003-05-28

Applicant: Renesas Technology Corp.

Inventor： Chuma Nagao ,  Hiroshi Ueki

IPC: G06F009/44

CPC classification number: G06F9/3804 ,  G06F9/3842 ,  G06F9/3885

Abstract: A microprocessor is provided with two queue buffers, one for storing prefetched non branch instructions and the other for storing prefetched branch target instructions, and a plurality of process stages. The process stages are divided into one last process stage and other process stages those form two different paths. Non branch instructions are processed in one path and branch target instructions are processed in other path. The paths are changed based on whether branch condition is met or not.

Abstract translation: 微处理器具有两个队列缓冲器，一个用于存储预取的非分支指令，另一个用于存储预取的分支目标指令，以及多个处理阶段。 过程阶段分为最后一个过程阶段和其他形成两个不同路径的过程阶段。 非分支指令在一个路径中处理，分支目标指令在其他路径中处理。 路径根据是否满足分支条件而改变。

公开(公告)号：US20040108559A1

公开(公告)日：2004-06-10

申请号：US10673789

申请日：2003-09-30

Applicant: Renesas Technology Corp.

Inventor： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC: H01L029/76

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

Abstract translation: 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US20040108534A1

公开(公告)日：2004-06-10

申请号：US10455325

申请日：2003-06-06

Applicant: Renesas Technology Corp.

Inventor： Takaaki Tsunomura ,  Masahiko Takeuchi

IPC: H01L027/108

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A storage node in a capacitor of a semiconductor device is formed of: an inner conductor in a columnar form having bottom, side and top surfaces; and an outer conductor, located on the bottom (between the bottom surface and the semiconductor substrate), side and top surfaces of the inner conductor, having a different material from that of the inner conductor. The outer conductor is formed of a metal film such as of Ru having a film thickness of about 40 nm to 80 nm. The inner conductor is formed of a film, such as a TiN film, a TaN film, a WN film or the like, having a high adhesion to the metal film such as of Ru. With this configuration, it is possible to provide a semiconductor device provided with a capacitor of which the capacitance is obtained.

Abstract translation: 半导体器件的电容器中的存储节点由具有底部，侧面和顶部表面的柱状形式的内部导体形成; 以及位于底部（底面和半导体衬底之间），内部导体的侧表面和顶表面之间的外部导体，其具有与内部导体不同的材料。 外导体由膜厚为约40nm至80nm的诸如Ru的金属膜形成。 内部导体由诸如RuN的金属膜具有高粘附性的诸如TiN膜，TaN膜，WN膜等的膜形成。 利用这种配置，可以提供一种设置有获得电容的电容器的半导体器件。

公开(公告)号：US20040107086A1

公开(公告)日：2004-06-03

申请号：US10700670

申请日：2003-11-05

Applicant: Renesas Technology Corp.

Inventor： Akira Yoshida ,  Masanori Kurimoto

IPC: G06F017/50

CPC classification number: G06F17/5022

Abstract: A logic simulation apparatus is provided with a circuit dividing unit (6) that selects and defines logic cones each of which carries out a logic operation in synchronization with one clock domain as target portions to be speeded up from logic cones extracted by a logic cone extracting unit (5), and that defines logic cons each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up, and a logic compressing unit (7) that compresses the logic of each of the target portions, and performs a logic simulation on each of the target portions whose logic is compressed and also on performs a logic simulation on each of the nontarget portions.

Abstract translation: 逻辑模拟装置具有电路划分单元（6），该电路划分单元（6）选择并定义逻辑锥，每个逻辑锥与一个时钟域同步地执行逻辑运算，作为从由逻辑锥提取提取的逻辑锥加速的目标部分 单元（5），并且其定义逻辑缺点，每个逻辑电路基于多个时钟域执行不被加速的非目标部分的逻辑运算;以及逻辑压缩单元（7），其压缩每个 目标部分，并对其逻辑被压缩的每个目标部分执行逻辑模拟，并且还对每个非目标部分执行逻辑模拟。

公开(公告)号：US20040106255A1

公开(公告)日：2004-06-03

申请号：US10448352

申请日：2003-05-30

Applicant: Renesas Technology Corp.

Inventor： Noriyuki Mitsuhira

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534

Abstract: A rewriting endurance of a flash memory is made to improve. A first interlayer insulating film (10) is formed on a flash memory cell which is formed in a memory element region on a semiconductor substrate (100). At this time, a furnace anneal is added as a heat treatment after a NSG layer (16) which is a top layer of the first interlayer insulating film (10) is formed, instead of a heat treatment in a short time by means of a lamp anneal. According to it, a stress which is impressed on the flash memory cell is relaxed, and a rewriting endurance is improved. Moreover, the furnace anneal is added after a first and a second aluminum wirings (21 and 31) are formed. Furthermore, when a second and a third interlayer insulating films (20 and 30) are formed, a deposition temperature of plasma TEOS layers (23 and 33) is set to be identical with a temperature of HDP layers (22 and 32) at that time. According to it, in the same manner, the rewriting endurance of the flash memory cell is improved.

Abstract translation: 闪存的重写耐久性得到提高。 第一层间绝缘膜（10）形成在形成在半导体衬底（100）上的存储元件区域中的闪存单元上。 此时，在形成第一层间绝缘膜（10）的顶层的NSG层（16）之后，加热炉退火，而不是在短时间内通过热处理 灯退火。 据此，放松了对闪存单元印象的压力，提高了重写耐力。 此外，在形成第一和第二铝布线（21和31）之后添加炉退火。 此外，当形成第二和第三层间绝缘膜（20,30）时，等离子体TEOS层（23和33）的沉积温度被设定为与此时的HDP层（22和32）的温度相同 。 据此，以相同的方式，提高了闪存单元的重写耐久性。

公开(公告)号：US20040103384A1

公开(公告)日：2004-05-27

申请号：US10431535

申请日：2003-05-08

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Genichi Tanaka

IPC: G06F017/50

CPC classification number: G06F17/5036

Abstract: A category classification unit determines a net of interest from nets that show information on the connection between cells defined in logical netlist information, searches the net of interest and the nets adjacent the net of interest in layout information, and classifies the net of interest and the adjacent nets into categories set while attention is paid to how potentials of the adjacent nets operate relatively to the potential of the net of interest defined in a constraint, based on the logical netlist information and logical information in a library. A parasitic element extraction unit extracts parasitic elements of extraction elements defined in the constraint for each of the categories into which the nets are classified by the category classification unit, and outputs connection information including the parasitic elements.

Abstract translation: 类别分类单元确定来自网络的兴趣净值，其显示关于在逻辑网表信息中定义的小区之间的连接的信息，在兴趣网中搜索与净利息的网络相关联的布局信息，并且将兴趣网和 基于逻辑网表信息和图书馆中的逻辑信息，相邻网络被注意到相关网络的电位如何相对于在约束中定义的兴趣点的潜力相对运行。 寄生元件提取单元通过类别分类单元提取由网络分类的每个类别的约束中定义的提取元素的寄生元素，并输出包括寄生元素的连接信息。

公开(公告)号：US20040103328A1

公开(公告)日：2004-05-27

申请号：US10702448

申请日：2003-11-07

Applicant: Renesas Technology Corp. ,  Renesas Northern Japan Semiconductor, Inc. ,  Hitachi Device Engineering Co., Ltd.

Inventor： Toru Ichien ,  Wataru Yamaguchi ,  Masae Sasakawa ,  Mamoru Wakabayashi

IPC: G06F001/26

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/325 ,  G06F1/3275 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/152

Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

Abstract translation: 这里公开了一种半导体数据处理装置，其在待机时间和操作时间实现低功耗，并且加快了接口操作。 半导体数据处理装置可以将非易失性存储装置连接到主机系统的通用总线。 数据处理装置响应于通用总线的状态进入主动或待机状态。 在待机状态下，数据处理装置停止内部时钟信号并向每个对象施加衬底偏置电压，以便抑制潜在的次阈值泄漏电流。 该偏置电压也被施加到中央处理单元和可重写非易失性存储器，用于存储要由中央处理单元执行的控制程序。 当接口控制器和数据传输控制器以2n位为单位输入/输出并行数据时，中央处理单元以n位为单位处理数据。

公开(公告)号：US20040102048A1

公开(公告)日：2004-05-27

申请号：US10457588

申请日：2003-06-10

Applicant: Renesas Technology Corp.

Inventor： Atsumi Yamaguchi

IPC: H01L021/311

CPC classification number: H01L21/0338 ,  H01L21/0273 ,  H01L21/0331 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139

Abstract: According to the present invention, in a method for manufacturing a semiconductor device, an underlayer film is formed on a substrate. A resist pattern is formed on the underlayer film. A spin-on glass film is formed on the underlayer film and the resist pattern so as to cover the resist pattern. The resist pattern is removed to produce a reversal pattern in the spin-on glass film. The underlayer film is etched by using the spin-on glass film as a mask to form a fine pattern.

Abstract translation: 根据本发明，在半导体装置的制造方法中，在基板上形成下层膜。 在下层膜上形成抗蚀剂图案。 在下层膜和抗蚀剂图案上形成旋涂玻璃膜以覆盖抗蚀剂图案。 去除抗蚀剂图案以在旋涂玻璃膜中产生反转图案。 通过使用旋涂玻璃膜作为掩模来蚀刻下层膜，以形成精细图案。