公开(公告)号：US20210200468A1

公开(公告)日：2021-07-01

申请号：US16730092

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.

公开(公告)号：US10535393B1

公开(公告)日：2020-01-14

申请号：US16041778

申请日：2018-07-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G11C11/406 ,  G11C11/409

Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

公开(公告)号：US20180018291A1

公开(公告)日：2018-01-18

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US12282439B2

公开(公告)日：2025-04-22

申请号：US17100254

申请日：2020-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F3/06 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US12265732B1

公开(公告)日：2025-04-01

申请号：US18375030

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jean J. Chittilappilly ,  Kevin M. Brandl ,  Jing Wang ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.

公开(公告)号：US12253961B2

公开(公告)日：2025-03-18

申请号：US16728114

申请日：2019-12-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen

IPC: G06F13/16 ,  G06F12/1009 ,  G11C8/12 ,  G11C11/406

Abstract: Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

公开(公告)号：US12158827B2

公开(公告)日：2024-12-03

申请号：US18091163

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20

Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.

公开(公告)号：US12038856B2

公开(公告)日：2024-07-16

申请号：US17961613

申请日：2022-10-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Brendan T. Mangan

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F13/1668 ,  G06F9/30043 ,  G06F12/0246 ,  G06F12/1009 ,  G06F13/1605

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US20240202289A1

公开(公告)日：2024-06-20

申请号：US18081540

申请日：2022-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： David Kaplan ,  Kedarnath Balakrishnan

IPC: G06F21/10 ,  G06F9/455

CPC classification number: G06F21/10 ,  G06F9/45558 ,  G06F2009/45587

Abstract: An electronic device includes a memory and controller circuitry. The controller circuitry, responsive to a read request to read encrypted data stored in the memory, acquires, from metadata stored with the encrypted data in the memory, an ownership identifier identifying a type of writing entity that stored the encrypted data in the memory. The controller circuitry uses the ownership identifier to control whether, when responding to the read request, data decrypted from the encrypted data is returned or substitute data is returned instead of data decrypted from the encrypted data.

公开(公告)号：US11704183B2

公开(公告)日：2023-07-18

申请号：US17544074

申请日：2021-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

CPC classification number: G06F11/0772 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/1004 ,  G06F11/1068 ,  H03M13/29

Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.