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公开(公告)号：US20220206946A1
公开(公告)日：2022-06-30
申请号：US17135657
申请日：2020-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Brandon K. Potter , Marko Scrbak , Sergey Blagodurov , Kishore Punniyamurthy , Nathaniel Morris
IPC: G06F12/0817
Abstract: Method and apparatus monitor eviction conflicts among cache directory entries in a cache directory and produce cache directory victim entry information for a memory manager. In some examples, the memory manager reduces future cache directory conflicts by changing a page level physical address assignment for a page of memory based on the produced cache directory victim entry information. In some examples, a scalable data fabric includes hardware control logic that performs the monitoring of the eviction conflicts among cache directory entries in the cache directory and produces the cache directory victim entry information.
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公开(公告)号：US20220156167A1
公开(公告)日：2022-05-19
申请号：US17588779
申请日：2022-01-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
IPC: G06F11/20
Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
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公开(公告)号：US20200379820A1
公开(公告)日：2020-12-03
申请号：US16425881
申请日：2019-05-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexandru Dutu , Sergey Blagodurov , Anthony T. Gutierrez , Matthew D. Sinclair , David A. Wood , Bradford M. Beckmann
Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.
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公开(公告)号：US10318153B2
公开(公告)日：2019-06-11
申请号：US14576912
申请日：2014-12-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Mitesh Ramesh Meswani , Gabriel H. Loh , Mauricio Breternitz, Jr. , Mark Richard Nutter , John Robert Slice , David Andrew Roberts , Michael Ignatowski , Mark Henry Oskin
IPC: G06F3/06
Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g., computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.
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公开(公告)号：US10261916B2
公开(公告)日：2019-04-16
申请号：US15361335
申请日：2016-11-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Amro Awad , Sergey Blagodurov , Arkaprava Basu , Mark H. Oskin , Gabriel H. Loh , Andrew G. Kegel , David S. Christie , Kevin J. McGrath
IPC: G06F12/10 , G06F12/1036 , G06F12/1009 , G06F12/1027
Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.
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Patent Agency Ranking
公开(公告)号：US10121555B2
公开(公告)日：2018-11-06
申请号：US15267092
申请日：2016-09-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Amro Awad , Sergey Blagodurov
Abstract: A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.
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公开(公告)号：US10055359B2
公开(公告)日：2018-08-21
申请号：US15040195
申请日：2016-02-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Gabriel H. Loh , John R. Slice
IPC: G06F12/00 , G06F12/122 , G06F3/06
Abstract: The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. During operation, a system runtime in the computer system identifies an object to be stored in the multi-level memory hierarchy. The system runtime then determines, based on one or more attributes of the object, that the object is to be pinned in a level of the multi-level memory hierarchy. The system runtime then pins the object in the level of the multi-level memory hierarchy. In the described embodiments, the pinning includes hard pinning and soft pinning, which are each associated with corresponding retention policies for pinned objects.
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公开(公告)号：US09965329B2
公开(公告)日：2018-05-08
申请号：US14880713
申请日：2015-10-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov
CPC classification number: G06F9/5044 , G06F9/5038 , G06F9/505 , G06F2209/501
Abstract: The methods and apparatus can assign processing core workloads to processing cores from a heterogeneous instruction set architectures (ISA) pool of available processing cores based on processing core metric results. For example, the method and apparatus can obtain processing core metric results for one or more processing cores, such as processing cores within general purpose processors, from a heterogeneous ISA pool of available processing cores. The method and apparatus can also obtain one or more processing core workloads, such as software applications or software processes, from a pool of available processing core workloads to be assigned. The method and apparatus can then assign one or more processing core workloads that have higher priority than others from the pool of available processing core workloads to a processing core from the heterogeneous ISA pool of available processing cores based on its processing core metric result.
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公开(公告)号：US09934148B2
公开(公告)日：2018-04-03
申请号：US14747967
申请日：2015-06-23
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Roberts , Sergey Blagodurov
IPC: G06F12/10 , G06F12/0862
CPC classification number: G06F12/0862 , G06F2212/6024
Abstract: A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.
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公开(公告)号：US20170102971A1
公开(公告)日：2017-04-13
申请号：US14880713
申请日：2015-10-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov
IPC: G06F9/50
CPC classification number: G06F9/5044 , G06F9/5038 , G06F9/505 , G06F2209/501
Abstract: The methods and apparatus can assign processing core workloads to processing cores from a heterogeneous instruction set architectures (ISA) pool of available processing cores based on processing core metric results. For example, the method and apparatus can obtain processing core metric results for one or more processing cores, such as processing cores within general purpose processors, from a heterogeneous ISA pool of available processing cores. The method and apparatus can also obtain one or more processing core workloads, such as software applications or software processes, from a pool of available processing core workloads to be assigned. The method and apparatus can then assign one or more processing core workloads that have higher priority than others from the pool of available processing core workloads to a processing core from the heterogeneous ISA pool of available processing cores based on its processing core metric result.
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