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    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT
    62.
    发明申请
    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT 审中-公开

    公开(公告)号：US20170371719A1

    公开(公告)日：2017-12-28

    申请号：US15192784

    申请日：2016-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Abhinandan Majumdar ,  Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Yasuko Eckert

    IPC: G06F9/50 ,  G06F1/32

    CPC classification number: G06F9/4893 ,  G06F1/206 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

    Abstract: Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.

    PRUNING OF LOW POWER STATE INFORMATION FOR A PROCESSOR
    66.
    发明申请
    PRUNING OF LOW POWER STATE INFORMATION FOR A PROCESSOR 有权
    处理器的低功率状态信息的调整

    公开(公告)号：US20160246360A1

    公开(公告)日：2016-08-25

    申请号：US14630687

    申请日：2015-02-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Derek Hower ,  Marc Orr

    IPC: G06F1/32

    CPC classification number: G06F1/3293 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information stored to memory.

    Abstract translation: 处理器基于由软件提供的信息来修剪状态信息，从而减少在处理器进入低功率状态之前要存储的状态信息量。 诸如在处理器执行的操作系统或应用程序的软件将处理器的一个或多个寄存器指示为不再有用的存储数据。 当准备进入低功率状态时，处理器从存储到存储器的状态信息中省略指示的寄存器。

    TRAFFIC RATE CONTROL FOR INTER-CLASS DATA MIGRATION IN A MULTICLASS MEMORY SYSTEM
    68.
    发明申请
    TRAFFIC RATE CONTROL FOR INTER-CLASS DATA MIGRATION IN A MULTICLASS MEMORY SYSTEM 有权
    用于多行存储器系统中的类间数据迁移的交通费率控制

    公开(公告)号：US20160170919A1

    公开(公告)日：2016-06-16

    申请号：US14569825

    申请日：2014-12-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Yasuko Eckert

    IPC: G06F13/16 ,  G06F11/34 ,  G06F12/02

    CPC classification number: G06F13/1694 ,  G06F11/3414 ,  G06F12/023 ,  G06F13/161 ,  G06F2212/1044 ,  Y02D10/14

    Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.

    Abstract translation: 系统包括多个存储器类别以及耦合到多个存储器类别的一个或多个处理单元的集合。 该系统还包括数据迁移控制器，用于基于与业务速率相关联的净利益度量来选择业务速率作为用于在多个存储器类之间传送数据的最大业务速率，并且执行用于在数据传输之间传送数据的最大业务速率 多个存储器类。

    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING
    70.
    发明申请
    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING 有权
    放弃进入和退出预测功率增益

    公开(公告)号：US20150370311A1

    公开(公告)日：2015-12-24

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32 ,  G06N5/04

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

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