公开(公告)号：US20210311800A1

公开(公告)日：2021-10-07

申请号：US17350874

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Anil Rao ,  Debendra Das Sharma

IPC: G06F9/50 ,  G06F9/4401 ,  G06F9/48 ,  H04L29/08

Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

公开(公告)号：US11086520B2

公开(公告)日：2021-08-10

申请号：US16510106

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Balint Fleischer ,  Debendra Das Sharma ,  Raj K. Ramanujan

IPC: G06F3/06 ,  H04L29/08 ,  H04L12/24

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US20210234946A1

公开(公告)日：2021-07-29

申请号：US17229763

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L29/06 ,  G06F13/42

Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

公开(公告)号：US20210119730A1

公开(公告)日：2021-04-22

申请号：US17134240

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Swadesh Choudhary

IPC: H04L1/00

Abstract: Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.

公开(公告)号：US20210050941A1

公开(公告)日：2021-02-18

申请号：US17086085

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

IPC: H04L1/00 ,  H03M13/09

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

公开(公告)号：US20210013999A1

公开(公告)日：2021-01-14

申请号：US17031822

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Mahesh Wagh

IPC: H04L1/00 ,  H04L12/833

Abstract: Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.

公开(公告)号：US10854548B2

公开(公告)日：2020-12-01

申请号：US16236136

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Adel A. Elsherbini ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.

公开(公告)号：US20200211965A1

公开(公告)日：2020-07-02

申请号：US16236136

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Adel A. Elsherbini ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.

公开(公告)号：US20200186414A1

公开(公告)日：2020-06-11

申请号：US16788434

申请日：2020-02-12

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L12/24 ,  H04L29/06 ,  H04L12/26

Abstract: In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

公开(公告)号：US10678736B2

公开(公告)日：2020-06-09

申请号：US15761401

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/366 ,  G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.