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公开(公告)号：US20190115951A1
公开(公告)日：2019-04-18
申请号：US16206919
申请日：2018-11-30
Applicant: Intel Corporation
Inventor： Henning Braunisch , Georgios Dogiamis , Jeff C. Morriss , Hyung-Jin Lee , Richard Dischler , Ajay Balankutty , Telesphor Kamgaing , Said Rami
Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.
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公开(公告)号：US20150089107A1
公开(公告)日：2015-03-26
申请号：US14558942
申请日：2014-12-03
Applicant: Intel Corporation
Inventor： David J. Harriman , Jeff C. Morriss
CPC classification number: G06F13/423 , G06F1/12 , G06F11/08 , G06F13/4291 , G08C25/00 , H04L1/0061 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有发送逻辑的主机控制器，用于将数据准备到分组中，以沿着互连进行通信并发送分组。 该分组可以包括具有第一预定值的前导码部分，包括数据的内容部分，并且具有多个符号，每个符号包括与数据分开的开始位，包括内容部分的反转版本的错误检测部分，以及 后同步码部分具有第二预定值。 描述和要求保护其他实施例。
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公开(公告)号：US11386033B2
公开(公告)日：2022-07-12
申请号：US17121534
申请日：2020-12-14
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L25/065 , G06F13/42 , H01L23/538
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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公开(公告)号：US10678736B2
公开(公告)日：2020-06-09
申请号：US15761401
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/366 , G06F13/40 , H01L25/065 , G06F13/42 , H01L23/538
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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公开(公告)号：US10396036B2
公开(公告)日：2019-08-27
申请号：US15774257
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Yu Amos Zhang , Zhiguo Qian , Kemal Aygun , Yidnekachew S. Mekonnen , Gregorio R. Murtagian , Sanka Ganesan , Eduard Roytman , Jeff C. Morriss
IPC: H01L23/48 , H01L23/538 , H01L23/552 , H01L23/66 , H01L23/498 , H01L23/50 , H01L25/065
Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.
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Patent Agency Ranking
公开(公告)号：US11108433B2
公开(公告)日：2021-08-31
申请号：US16206919
申请日：2018-11-30
Applicant: Intel Corporation
Inventor： Henning Braunisch , Georgios Dogiamis , Jeff C. Morriss , Hyung-Jin Lee , Richard Dischler , Ajay Balankutty , Telesphor Kamgaing , Said Rami
Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.
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公开(公告)号：US20210097015A1
公开(公告)日：2021-04-01
申请号：US17121534
申请日：2020-12-14
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L23/538 , H01L25/065 , G06F13/42
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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公开(公告)号：US20180276164A1
公开(公告)日：2018-09-27
申请号：US15761401
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L25/065 , H01L23/538
CPC classification number: G06F13/4027 , G06F13/4022 , G06F13/405 , G06F13/4265 , H01L23/5386 , H01L25/0655 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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公开(公告)号：US09524265B2
公开(公告)日：2016-12-20
申请号：US14558942
申请日：2014-12-03
Applicant: Intel Corporation
Inventor： David J. Harriman , Jeff C. Morriss
CPC classification number: G06F13/423 , G06F1/12 , G06F11/08 , G06F13/4291 , G08C25/00 , H04L1/0061 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有发送逻辑的主机控制器，用于将数据准备到分组中，以沿着互连进行通信并发送分组。 该分组可以包括具有第一预定值的前导码部分，包括数据的内容部分，并且具有多个符号，每个符号包括与数据分开的开始位，包括内容部分的反转版本的错误检测部分，以及 后同步码部分具有第二预定值。 描述和要求保护其他实施例。
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公开(公告)号：US20240020259A1
公开(公告)日：2024-01-18
申请号：US18352785
申请日：2023-07-14
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L25/065 , G06F13/42 , H01L23/538
CPC classification number: G06F13/4027 , H01L25/0655 , G06F13/4265 , G06F13/4022 , G06F13/405 , H01L23/5386 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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