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    PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE
    66.
    发明申请
    PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE 有权

    公开(公告)号：US20220238411A1

    公开(公告)日：2022-07-28

    申请号：US17718031

    申请日：2022-04-11

    Applicant: Intel Corporation

    Inventor： Feras EID ,  Johanna M. SWAN ,  Sergio CHAN ARGUEDAS ,  John J. BEATTY

    IPC: H01L23/367 ,  H01L21/48 ,  H01L49/02

    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

    ELECTROMAGNETIC INTERFERENCE SHIELD CREATED ON PACKAGE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
    68.
    发明申请
    ELECTROMAGNETIC INTERFERENCE SHIELD CREATED ON PACKAGE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING 审中-公开

    公开(公告)号：US20200312782A1

    公开(公告)日：2020-10-01

    申请号：US16651949

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Feras EID ,  Henning BRAUNISCH ,  Shawna M. LIFF ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN

    IPC: H01L23/552 ,  H01L21/48 ,  H01L23/04 ,  H01L23/10 ,  H01L23/498 ,  H01L23/00

    Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.

    DIE BACKSIDE STRUCTURES FOR ENHANCING LIQUID COOLING OF HIGH POWER MULTI-CHIP PACKAGE (MCP) DICE
    69.
    发明申请
    DIE BACKSIDE STRUCTURES FOR ENHANCING LIQUID COOLING OF HIGH POWER MULTI-CHIP PACKAGE (MCP) DICE 审中-公开

    公开(公告)号：US20200176352A1

    公开(公告)日：2020-06-04

    申请号：US16612340

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Je-Young CHANG ,  Chandra M. JHA ,  Shankar DEVASENATHIPATHY ,  Feras EID ,  John C. JOHNSON

    IPC: H01L23/427 ,  H01L23/26 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48 ,  F28D15/02

    Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

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