公开(公告)号：US20240171593A1

公开(公告)日：2024-05-23

申请号：US17990091

申请日：2022-11-18

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Vuk Lesi ,  Manoj Sastry

IPC: H04L9/40 ,  H04J3/06

CPC classification number: H04L63/1416 ,  H04J3/0658 ,  H04L63/1466

Abstract: Techniques include an apparatus to retrieve a first parameter for the IDS to monitor a device for a time-synchronized network. The first parameter may represent a number of messages the IDS needs to analyze in order to detect a security attack. The messages may comprise time information to synchronize a clock for a device to a network time for a time-synchronized network. The processor circuitry may retrieve a second parameter for a time sensitive application. The second parameter may represent a defined amount of time error tolerated by the time sensitive application, and determine a third parameter for the IDS based on the first and second parameters. The third parameter may represent a defined frequency to receive a number of messages with time information in order to detect the security attack on the device within a defined time interval. Other embodiments are described and claimed.

公开(公告)号：US20240143020A1

公开(公告)日：2024-05-02

申请号：US17974113

申请日：2022-10-26

Applicant: Intel Corporation

Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Marcio Juliato ,  Manoj Sastry

IPC: G06F1/12 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/08

Abstract: An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise: a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager; and a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to take over operations for the clock manager in response to the alert from the detector. Other embodiments are described and claimed.

公开(公告)号：US11792191B2

公开(公告)日：2023-10-17

申请号：US17650767

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Rafael Misoczki ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08

CPC classification number: H04L63/0869 ,  H04L9/0852 ,  H04L9/3242 ,  H04L9/3265

Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.

公开(公告)号：US11665178B2

公开(公告)日：2023-05-30

申请号：US16727638

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Christopher N. Gutierrez ,  Shabbir Ahmed ,  Marcio Juliato ,  Manoj Sastry ,  Liuyang L. Yang ,  Xiruo Liu

IPC: H04L29/06 ,  H04L9/40 ,  H04L12/40 ,  G06N20/20

CPC classification number: H04L63/1408 ,  G06N20/20 ,  H04L12/40032 ,  H04L63/0227 ,  H04L63/1425 ,  H04L63/1441 ,  H04L2012/40273

Abstract: Logic may reduce the latency and increase the confidence in message time series (MTS) intrusion detection systems (IDSs). Logic may capture traffic on an in-vehicle network bus during a first traffic window. Logic may filter the traffic within the first traffic window to determine more than one observation window, wherein the more than observation window comprises at least a first observation window and a second observation window. Logic may evaluate the more than one observation window to determine a first output based on a first observation window and a second output based on a second observation window, the first and second outputs to indicate if an intrusion is detected. Logic may determine, based on a combination of the outputs, that the traffic during the first traffic window comprises an intrusion. Logic may output an indication of the intrusion.

公开(公告)号：US11575521B2

公开(公告)日：2023-02-07

申请号：US16455967

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  David Wheeler ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/06

Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.

公开(公告)号：US20220416998A1

公开(公告)日：2022-12-29

申请号：US17356168

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Dumitru-Daniel Dinu ,  Joseph Friel ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/06 ,  G06F21/72 ,  H04L9/00

Abstract: In one example an apparatus comprises an input state register, and a first round secure hash algorithm (SHA) datapath circuit communicatively coupled to the input state register and a second round secure hash algorithm (SHA) datapath circuit communicatively coupled to the first round secure hash datapath circuit, the first round secure has algorithm (SHA) datapath circuit and the second round secure hash algorithm (SHA) datapath circuit each comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step calculation, a third section to perform a π step of the SHA calculation, a fourth section to perform a χ step of the SHA calculation, and a fifth section to perform a ι step of the SHA calculation.

公开(公告)号：US20220368537A1

公开(公告)日：2022-11-17

申请号：US17816148

申请日：2022-07-29

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: H04L9/32 ,  G06F21/72

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US20220355807A1

公开(公告)日：2022-11-10

申请号：US17858676

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Liuyang Yang ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez

IPC: B60W50/00 ,  B60W30/14 ,  B60W30/12 ,  H04W4/40 ,  B60W30/09

Abstract: Systems, apparatus, methods, and techniques for an ego vehicle to respond to detecting misbehaving information from remote vehicles are provided. An ego vehicle, in addition to reporting misbehaving vehicles to a misbehavior authority via a vehicle-to-anything communication network, can, take additional actions based in part on how confident the ego vehicle is about the evidence of misbehavior. Where the confidence is high the ego vehicle can simply discard the misbehaving data and provide an alternative estimate for such data from alternative sources. Where the confidence is not high the ego vehicle can request assistance from neighboring vehicles and roadside units to provide independent estimates of the data to increase confidence in the evidence of misbehavior.

公开(公告)号：US11489661B2

公开(公告)日：2022-11-01

申请号：US16909648

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry

IPC: H04L29/06 ,  H04L9/06 ,  G06N10/00 ,  H04L9/08 ,  H04L9/40

Abstract: An apparatus comprises an input register to receive a transport layer data packet, an encryption/decryption pipeline communicatively coupled to the input register, comprising a first section comprising a set of advanced encryption standard (AES) engines including at least a first AES engine to perform encryption and/or decryption operations on input data from the at least a portion of a transport layer data packet, a second AES engine to determine an authentication key, and a third AES engine to determine an authentication tag mask, a second section comprising a first set of Galois field multipliers comprising at least a first Galois field multiplier to compute a first multiple of the authentication key, a third section comprising a second set of Galois field multipliers to compute a first partial authentication tag, and a fourth section comprising a processing circuitry to compute a second partial authentication tag and a final authentication tag.

公开(公告)号：US20220321321A1

公开(公告)日：2022-10-06

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72 ,  G06N3/08 ,  H04L9/06

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.