公开(公告)号：US20200150741A1

公开(公告)日：2020-05-14

申请号：US16661803

申请日：2019-10-23

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F1/3234 ,  G06F1/329 ,  G06F9/46

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

公开(公告)号：US10579121B2

公开(公告)日：2020-03-03

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F15/16 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US10459509B2

公开(公告)日：2019-10-29

申请号：US15483580

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F15/00 ,  G06F1/3234 ,  G06F1/329 ,  G06F9/46

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

公开(公告)号：US10402224B2

公开(公告)日：2019-09-03

申请号：US15860708

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Kamlesh Pillai ,  James Valerio ,  Joydeep Ray ,  Abhishek Appu

IPC: G06F9/48 ,  G06F9/54 ,  G06T1/20 ,  G06F9/22 ,  G06T15/00

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

公开(公告)号：US10319070B2

公开(公告)日：2019-06-11

申请号：US16120591

申请日：2018-09-04

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Prasoonkumar P. Surti ,  Kamal Sinha ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Bhushan M. Borole ,  Wenyin Fu

IPC: G06F12/00 ,  G06T1/60 ,  G06T15/00 ,  G06T1/20

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

公开(公告)号：US10268596B2

公开(公告)日：2019-04-23

申请号：US15493267

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Kiran C. Veernapu

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06T1/20 ,  G06T1/60

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.

公开(公告)号：US10261859B2

公开(公告)日：2019-04-16

申请号：US15489041

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray

IPC: G06F11/10 ,  G11C29/52 ,  G06T15/00 ,  G06T1/60 ,  G06T11/00

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190026856A1

公开(公告)日：2019-01-24

申请号：US16120591

申请日：2018-09-04

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Prasoonkumar P. Surti ,  Kamal Sinha ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Bhushan M. Borole ,  Wenyin Fu

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

公开(公告)号：US20180307286A1

公开(公告)日：2018-10-25

申请号：US15493574

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F1/20 ,  G05B19/05

CPC classification number: G06F1/206 ,  G05B19/054 ,  G05B2219/15097

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285230A1

公开(公告)日：2018-10-04

申请号：US15477031

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F11/30 ,  G06F1/32 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34

CPC classification number: G06F11/3058 ,  G05F1/10 ,  G05F1/571 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/322 ,  G06F11/328 ,  G06F11/3476

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.