公开(公告)号：US20240259182A1

公开(公告)日：2024-08-01

申请号：US18162856

申请日：2023-02-01

Applicant: Intel Corporation

Inventor： Santosh Ghosh

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: Techniques for implementing Advanced Encryption Standard (AES)-256 encryption. An implementation includes a time-shared round data path with a depth-2 pipeline that results in an atomic execution of two 14-round AES-256 encryption operations in 30 cycles while operating at the same high-frequency clock used for processing cores of a computing system. The technology described herein uses only two cycles of latency per round while supporting a very high maximum operating clock speed.

公开(公告)号：US12032486B2

公开(公告)日：2024-07-09

申请号：US17560360

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

IPC: G06F12/1027 ,  G06F9/38

CPC classification number: G06F12/1027 ,  G06F9/3818 ,  G06F2212/68

Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.

公开(公告)号：US20240223381A1

公开(公告)日：2024-07-04

申请号：US18157272

申请日：2023-01-20

Applicant: Intel Corporation

Inventor： Alan Hwang ,  Solmaz Ghaznavi ,  Santosh Ghosh

IPC: H04L9/32 ,  H04L9/30

CPC classification number: H04L9/3247 ,  H04L9/30 ,  H04L9/3236

Abstract: Techniques for performing digital signature verification are described. Digital signature verification circuitry includes a memory; and signature verification circuitry, including Secure Hash Algorithm (SHA) circuitry; message representative generator circuitry; tree verification circuitry; and hypertree verification circuitry.

公开(公告)号：US12026516B1

公开(公告)日：2024-07-02

申请号：US18145776

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30032

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotated XOR result.

公开(公告)号：US20240179160A1

公开(公告)日：2024-05-30

申请号：US18526456

申请日：2023-12-01

Applicant: Intel Corporation

Inventor： Marcio Rogerio Juliato ,  Shabbir Ahmed ,  Santosh Ghosh ,  Christopher Gutierrez ,  Manoj R. Sastry

IPC: H04L9/40 ,  H04L12/40

CPC classification number: H04L63/1416 ,  H04L12/40 ,  H04L12/40136 ,  H04L63/1466 ,  H04L2012/40215

Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.

公开(公告)号：US11917053B2

公开(公告)日：2024-02-27

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F7/503 ,  G06F9/3012 ,  H04L9/3247

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11777707B2

公开(公告)日：2023-10-03

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  G06F21/72 ,  G06F7/487 ,  G06F21/60 ,  G06N3/063 ,  G06N20/00 ,  G06N3/08

CPC classification number: H04L9/008 ,  G06F7/722 ,  G06N3/08 ,  H04L9/0618

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.

公开(公告)号：US11750402B2

公开(公告)日：2023-09-05

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F9/3877 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11722313B2

公开(公告)日：2023-08-08

申请号：US17014600

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30 ,  G06N10/00

CPC classification number: H04L9/3247 ,  G06N10/00 ,  H04L9/0618 ,  H04L9/0825 ,  H04L9/0852 ,  H04L9/0877 ,  H04L9/14 ,  H04L9/3073 ,  H04L9/0836 ,  H04L9/3239

Abstract: An apparatus comprises a plurality of hardware security modules, at least a first hardware security module in the plurality of hardware security modules comprising processing circuitry to generate a first plurality of pairs of cryptographic key pairs comprising a first plurality of private keys and a first plurality of public keys, forward the first plurality of public keys to a remote computing device, receive, from the remote computing device, a first plurality of ciphertexts, wherein each ciphertext in the plurality of ciphertexts represents an encryption of a cryptographic seed with a public key selected from the plurality of public keys, receive, from a subset of hardware security modules in the plurality of hardware security modules, a subset of private keys.

公开(公告)号：US20220417019A1

公开(公告)日：2022-12-29

申请号：US17356972

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Manoj Sastry

IPC: H04L9/30 ,  H04L9/14 ,  H04L9/06

Abstract: An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.