公开(公告)号：US20240220640A1

公开(公告)日：2024-07-04

申请号：US18148638

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Daniël Kuijsters ,  Christoph Dobraunig ,  Santosh Ghosh

IPC: G06F21/60 ,  G06F21/54 ,  G06F21/55

CPC classification number: G06F21/602 ,  G06F21/54 ,  G06F21/554

Abstract: In one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.

公开(公告)号：US20240104027A1

公开(公告)日：2024-03-28

申请号：US17953186

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Michael LeMay ,  David M. Durham

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F12/1441 ,  G06F12/1466

Abstract: In one embodiment, a processor includes a cache and a core. The core includes an execution unit and cryptographic computing circuitry to encrypt plaintext data output by the execution unit and store the encrypted data in the cache and decrypt encrypted data accessed from the cache and provide the decrypted data to the execution unit for processing. The encryption and decryption are based on both a stream cipher and a block cipher. In some embodiments, the encryption is based on providing an output of the stream cipher to the block cipher and the decryption is based on providing an output of the block cipher to the stream cipher.

公开(公告)号：US20230402077A1

公开(公告)日：2023-12-14

申请号：US18145095

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  Christoph Dobraunig ,  Rajat Agarwal ,  David M. Durham ,  Santosh Ghosh ,  Karanvir Grewal ,  Krystian Matusiewicz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.

公开(公告)号：US20250112761A1

公开(公告)日：2025-04-03

申请号：US18477335

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： David M. Durham ,  Christoph Dobraunig

IPC: H04L9/06

Abstract: Techniques for preventing replay for compressible data are described. In certain examples, a computing system includes a memory; an execution circuitry to execute an instruction to generate a memory request to read a data line from the memory; and a memory controller circuit to: determine that a field of the data line is not set to a conflict indicator value, determine that the field of the data line is set to a compressed indicator value, in response to the determinations, perform a hash of a compressed data field of the data line using a key to generate a tag, compare the tag generated by the hash to a corresponding tag field of the data line, and decompress the compressed data field of the data line, in response to the tag generated by the hash matching the corresponding tag field of the data line, to generate decompressed data.

公开(公告)号：US20240264837A1

公开(公告)日：2024-08-08

申请号：US18164738

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Christoph Dobraunig ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30029 ,  G06F9/30032

Abstract: Techniques are described for an instruction for a conditional rotate and XOR operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.

公开(公告)号：US20240211261A1

公开(公告)日：2024-06-27

申请号：US18145776

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30032

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotated XOR result.

公开(公告)号：US12254203B2

公开(公告)日：2025-03-18

申请号：US18145095

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  Christoph Dobraunig ,  Rajat Agarwal ,  David M. Durham ,  Santosh Ghosh ,  Karanvir Grewal ,  Krystian Matusiewicz

IPC: G06F3/06 ,  G11C7/24

Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.

公开(公告)号：US20240211268A1

公开(公告)日：2024-06-27

申请号：US18145801

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/3016 ,  G06F9/3802

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.

公开(公告)号：US20240211253A1

公开(公告)日：2024-06-27

申请号：US18145744

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry ,  Andrew H. Reinders ,  Regev Shemy ,  Qian Wang ,  Rotem Ohana Peretz ,  Wing Shek Wong ,  Wajdi Feghali

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/3016 ,  G06F9/3802

Abstract: A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.

公开(公告)号：US20250138829A1

公开(公告)日：2025-05-01

申请号：US19009066

申请日：2025-01-03

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/38 ,  G06F9/30

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.