公开(公告)号：US20190116023A1

公开(公告)日：2019-04-18

申请号：US16158659

申请日：2018-10-12

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: H04L9/00 ,  H04L9/06

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

公开(公告)号：US10256973B2

公开(公告)日：2019-04-09

申请号：US15283000

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Avinash L. Varna ,  Vikram B. Suresh ,  Sudhir K. Satpathy

IPC: H04L9/06 ,  H03K19/21 ,  H04L9/00 ,  G09C1/00 ,  G11C19/00

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

公开(公告)号：US20190044718A1

公开(公告)日：2019-02-07

申请号：US15982278

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Sudhir K. Satpathy ,  Manoj R. Sastry

IPC: H04L9/30 ,  G06F7/72 ,  G06F7/544

Abstract: In one embodiment, an apparatus includes: a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include: a multiplier circuit comprising a parallel combinatorial multiplier; and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.

公开(公告)号：US10164773B2

公开(公告)日：2018-12-25

申请号：US15282232

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sanu K. Mathew ,  Sudhir K. Satpathy

IPC: H04K1/00 ,  H04L9/06 ,  H03K19/20

Abstract: Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.

公开(公告)号：US10158485B2

公开(公告)日：2018-12-18

申请号：US14863769

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vinodh Gopal ,  Kirk S. Yap

IPC: H04L9/10 ,  G09C1/00 ,  H04L9/06 ,  G06F7/72

Abstract: A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.

公开(公告)号：US10129018B2

公开(公告)日：2018-11-13

申请号：US14939141

申请日：2015-11-12

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Vikram B. Suresh ,  Sanu K. Mathew

IPC: G06F21/72 ,  H04L9/06 ,  G06F21/60 ,  G06F9/30 ,  G06F9/38

Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic includes a message scheduling module selectively operating in one of a SHA mode or an SM3 mode to generate a sequence of message words based on an incoming message. The processing logic also includes a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words.

公开(公告)号：US09876509B2

公开(公告)日：2018-01-23

申请号：US15335705

申请日：2016-10-27

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Sudhir K. Satpathy ,  Sanu K. Mathew

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

Abstract: An example method to parallelize data decompression includes adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.

公开(公告)号：US20180006808A1

公开(公告)日：2018-01-04

申请号：US15196698

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sudhir K. Satpathy ,  Sanu K. Mathew

IPC: H04L9/06

CPC classification number: H04L9/0643 ,  G09C1/00 ,  H04L2209/12

Abstract: A processing system includes a processor to construct an input message comprising a plurality of padding bits and a hardware accelerator, communicatively coupled to the processor, comprising a first plurality of circuits to perform a stage-1 secure hash algorithm (SHA) hash based on the input message, wherein the hardware accelerator comprises a first data path coupled between a first reference node and a first input node of the first plurality of circuits to feed a first padding bit of the plurality of padding bits to the first input node.

公开(公告)号：US20180004242A1

公开(公告)日：2018-01-04

申请号：US15196712

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sudhir K. Satpathy ,  Sanu K. Mathew

IPC: G06F1/06 ,  H04L9/32

CPC classification number: G06F1/06 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125 ,  H04L2209/38

Abstract: A processing system includes a processor and a hardware accelerator, communicatively coupled to the processor, comprising a plurality of circuits to perform a plurality rounds of computation, wherein the plurality of circuits comprise a first set of level-sensitive latches enabled by a first clock signal to store data associated with a first round of the plurality of rounds of computation and a second set of level-sensitive latches enabled by a second clock signal to store data associated with a second round of the plurality of rounds of computation, and wherein a duty cycle of the first clock signal and a duty cycle of the second clock signal are non-overlapping.

公开(公告)号：US09825647B1

公开(公告)日：2017-11-21

申请号：US15278329

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  James D. Guilford ,  Vikram B. Suresh ,  Sanu K. Mathew ,  Vinodh Gopal

IPC: H03M7/34 ,  H03M7/30 ,  G06F9/30 ,  H03M7/42

CPC classification number: H03M7/3053 ,  G06F9/3016 ,  H03M7/3082 ,  H03M7/4037 ,  H03M7/42 ,  H03M7/6005 ,  H03M7/6029

Abstract: In one embodiment, an apparatus comprises a decompression engine to perform a non-speculative decode operation on a first portion of a first compressed payload comprising a first plurality of codes; and perform a speculative decode operation on a second portion of the first compressed payload, wherein the non-speculative decode operation and the speculative decode operation share at least one decode path and the non-speculative decode operation is to utilize bandwidth of the at least one decode path that is not used by the non-speculative decode operation.