公开(公告)号：US10734482B2

公开(公告)日：2020-08-04

申请号：US16097592

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/165 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/76 ,  H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L29/778 ,  H03K17/687 ,  H01L29/06

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

公开(公告)号：US20200212210A1

公开(公告)日：2020-07-02

申请号：US16648402

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke

IPC: H01L29/778 ,  H01L29/76 ,  H01L29/82 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8234

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

公开(公告)号：US20190341459A1

公开(公告)日：2019-11-07

申请号：US16306475

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC: H01L29/15 ,  H01L29/78 ,  G06N10/00 ,  H01L29/165 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.

公开(公告)号：US20190312128A1

公开(公告)日：2019-10-10

申请号：US16307724

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Adel A. Elsherbini

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/76 ,  H01L29/12

Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.

公开(公告)号：US10361353B2

公开(公告)日：2019-07-23

申请号：US15891518

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo

IPC: H01L29/06 ,  H01L39/14 ,  H01L39/22 ,  H01L29/12 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L39/24 ,  G06N10/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

公开(公告)号：US20190164077A1

公开(公告)日：2019-05-30

申请号：US16307970

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  James S. Clarke ,  David J. Michalak

IPC: G06N10/00 ,  G01R33/035

Abstract: Described herein are structures that include flux bias lines for controlling frequencies of qubits in quantum circuits. An exemplary structure includes a substrate, a qubit provided over a surface of the substrate, and a flux bias line provided below the surface of the substrate and configured to control the frequency of the qubit via a magnetic field generated as a result of a current flowing through the flux bias line. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190044044A1

公开(公告)日：2019-02-07

申请号：US15897712

申请日：2018-02-15

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Adel A. Elsherbini ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Hubert C. George ,  Stefano Pellerano

IPC: H01L39/02 ,  H01L39/22

Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.

公开(公告)号：US20190043989A1

公开(公告)日：2019-02-07

申请号：US16017942

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L23/522 ,  H01L29/06

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

公开(公告)号：US20190043919A1

公开(公告)日：2019-02-07

申请号：US16012815

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L27/18 ,  H01L39/22 ,  H01L49/02 ,  G06N99/00

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

公开(公告)号：US12245523B2

公开(公告)日：2025-03-04

申请号：US18301439

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC: H10N60/10 ,  G06N10/00 ,  H10N60/01 ,  H10N60/12 ,  H10N60/80

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.