公开(公告)号：US20250105095A1

公开(公告)日：2025-03-27

申请号：US18471356

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Bozidar Marinkovic ,  Benjamin Kriegel ,  Payam Amin ,  Dolly Natalia Ruiz Amador ,  Thomas Jacroux ,  Makram Abd El Qader ,  Tofizur RAHMAN ,  Xiandong Yang ,  Conor P. Puls

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

公开(公告)号：US20230197833A1

公开(公告)日：2023-06-22

申请号：US17558207

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Payam Amin ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/15 ,  H01L29/786 ,  H03K17/92 ,  G06N10/40

CPC classification number: H01L29/66977 ,  H01L29/158 ,  H01L29/78645 ,  H03K17/92 ,  G06N10/40 ,  H01L29/0665

Abstract: Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

公开(公告)号：US20220013658A1

公开(公告)日：2022-01-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20200279937A1

公开(公告)日：2020-09-03

申请号：US16645962

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Kanwaljit Singh ,  Nicole K. Thomas ,  Hubert C. George ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Payam Amin ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/165 ,  G06N10/00 ,  H01L29/423 ,  H01L27/088

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

公开(公告)号：US20190044050A1

公开(公告)日：2019-02-07

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/04 ,  H01L39/24 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US20250140748A1

公开(公告)日：2025-05-01

申请号：US18498519

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Payam Amin ,  Mandip Sibakoti ,  Bozidar Marinkovic ,  Tofizur RAHMAN ,  Conor P. Puls

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.

公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US20190334020A1

公开(公告)日：2019-10-31

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US20190043951A1

公开(公告)日：2019-02-07

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.