公开(公告)号：US20120268155A1

公开(公告)日：2012-10-25

申请号：US13266907

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2889 ,  G01R31/024 ,  Y10T29/49004

Abstract: Diagnostic tools for testing integrated circuit (IC) devices, and a method of making the same. The first diagnostic tool includes a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between proximal ends of contact members in the socket and contact pads on a printed circuit board (PCB). A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location external to the first interface. The electrical devices are electrically coupled to the conductive traces and programmed to provide one or more of continuity testing at the first interface or functionality of the IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a surrogate IC device.

Abstract translation: 用于测试集成电路（IC）器件的诊断工具及其制作方法。 第一诊断工具包括具有多个接触焊盘的第一顺应性印刷电路，其被配置为在插座中的接触构件的近端和印刷电路板（PCB）上的接触焊盘之间的第一界面处形成电互连。 多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。 多个电气设备被印刷在第一接合印刷电路上的位于第一接口外部的位置处。 电气设备电耦合到导电迹线并被编程为在IC器件的第一接口或功能性处提供一个或多个连续性测试。 第二诊断工具包括电耦合到替代IC器件的第二顺应印刷电路。

公开(公告)号：US20120061851A1

公开(公告)日：2012-03-15

申请号：US13319120

申请日：2010-06-07

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L24/50 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/42 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/552 ,  H01L24/86 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds

Abstract translation: 具有模拟线束的半导体封装。 衬底在第一表面上设置有多个第一焊盘，在第二表面上设置有多个第二焊盘。 每个第一焊盘电耦合到一个或多个第二焊盘。 至少一个半导体器件位于衬底的第一表面附近。 模拟线圈包括至少第一电介质层，其选择性地印刷以产生多个凹陷，以及位于凹槽中以形成第一和第二接触焊盘的导电材料以及电耦合第一和第二接触焊盘的电迹线。 第一接触焊盘电耦合到半导体器件上的端子，并且第二接触焊盘电耦合到衬底的第一表面上的第一焊盘。 包覆成型材料密封半导体器件和模拟引线

公开(公告)号：US20120056640A1

公开(公告)日：2012-03-08

申请号：US13319203

申请日：2010-06-28

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R31/28 ,  H05K3/10

CPC classification number: G01R1/0466 ,  G01R1/07314 ,  G01R1/0735 ,  G01R1/07378 ,  Y10T29/49155

Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

Abstract translation: 一种兼容的印刷电路半导体测试器接口，其在被测试的集成电路（IC）器件上的端子之间提供临时互连。 符合标准的印刷电路半导体测试器接口包括至少一个印刷有对应于目标电路几何形状的凹部的电介质层。 导电材料沉积在包括电路几何形状的凹槽的至少一部分中，以及可沿柔性印刷电路的第一表面接近的多个第一接触焊盘。 优选地，在电路几何形状上施加至少一个电介质覆盖层。 设置电介质覆盖层中的多个开口以允许IC器件上的端子和第一接触焊盘的电耦合。 用于测试IC器件的电气功能的测试电子器件电耦合到电路几何形状。

公开(公告)号：US20120056332A1

公开(公告)日：2012-03-08

申请号：US13318200

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/538 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/6836 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.

Abstract translation: 一种用于半导体器件的晶片级封装以及一种制造封装的方法。 至少一个电介质层被选择性地印刷在半导体器件的至少一部分上，形成与半导体器件上的多个电端子对准的第一凹槽。 在第一凹部中印刷导电材料，以在半导体器件上形成接触部件。 选择性地印刷至少一个电介质层以产生对应于目标电路几何形状的多个第二凹部。 导电材料印刷在第二凹槽的至少一部分中以产生电路几何形状。 电路几何形状包括适于电耦合到另一电路部件的多个暴露端子。 切割晶片以提供多个分立的封装半导体器件。

公开(公告)号：US20120044659A1

公开(公告)日：2012-02-23

申请号：US13318181

申请日：2010-05-25

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H01L21/6835 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/4664 ,  H05K3/4682 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.

Abstract translation: 一种兼容的印刷电路半导体封装，包括具有至少第一介电层的柔性印刷电路，所述第一介电层选择性地印刷在具有第一凹槽的 在第一凹部中印刷导电材料以形成可沿顺应性印刷电路的第一表面接触的接触部件。 至少一个半导体器件位于顺应印刷电路的第一表面附近。 接线将半导体器件上的端子电耦合到接触构件。 包覆成型材料将半导体器件和引线密封到兼容印刷电路的第一表面。 柔性印刷电路的第二表面上的接触焊盘电耦合到接触构件。

公开(公告)号：US20050099763A1

公开(公告)日：2005-05-12

申请号：US10992482

申请日：2004-11-17

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R1/067 ,  G01R1/073 ,  H05K3/32 ,  H02B1/00

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/06738 ,  G01R1/0735 ,  H01R12/523 ,  H01R12/62

Abstract: A method and apparatus for achieving a very fine pitch interconnect between a flexible circuit member and another circuit member with extremely co-planar electrical contacts that have a large range of compliance. An electrical interconnect assembly that can be used as a die-level test probe, a wafer probe, and a printed circuit probe is also disclosed. The second circuit member can be a printed circuit board, another flexible circuit, a bare-die device, an integrated circuit device, an organic or inorganic substrate, a rigid circuit and virtually any other type of electrical component. A plurality of electrical contacts are arranged in a housing. The electrical contacts may be arranged randomly or in a one or two-dimensional array. The housing acts as a receptacle to individually locate and generally align the electrical contacts, while preventing adjacent contacts from touching. The first ends of the electrical contacts are electrically coupled to a flexible circuit member. The second ends of the electrical contacts are free to electrically couple with one or more second circuit members without the use of solder.

Abstract translation: 一种用于在柔性电路部件与另一电路部件之间实现非常细间距互连的方法和装置，其具有具有大范围的柔量的非常共面的电触点。 还公开了可用作管芯级测试探针，晶片探针和印刷电路探针的电互连组件。 第二电路构件可以是印刷电路板，另一个柔性电路，裸露器件，集成电路器件，有机或无机衬底，刚性电路和实际上任何其它类型的电气部件。 多个电触头布置在壳体中。 电触点可以随机或以一维或二维阵列布置。 壳体用作插座以单独定位并大体上对准电触点，同时防止相邻的触点接触。 电触点的第一端电耦合到柔性电路部件。 电触点的第二端可自由地与一个或多个第二电路元件电耦合而不使用焊料。