公开(公告)号：US12222835B2

公开(公告)日：2025-02-11

申请号：US17575399

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  John David Porter

IPC: G06F11/30 ,  G11C5/14

Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.

公开(公告)号：US12183380B2

公开(公告)日：2024-12-31

申请号：US17362348

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C7/06 ,  G11C7/14 ,  G11C11/22 ,  G11C11/24

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US12131765B2

公开(公告)日：2024-10-29

申请号：US17898923

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22

CPC classification number: G11C11/2257

Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a word line to precharge the word line. A memory device may include voltage shaping circuitry and a memory controller. The memory controller may cause the voltage shaping circuitry to adjust a characteristic of a word line select control signal transmitted via the word line prior to the word line select control signal being transmitted to a memory cell.

公开(公告)号：US20240290379A1

公开(公告)日：2024-08-29

申请号：US18656156

申请日：2024-05-06

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US20240071454A1

公开(公告)日：2024-02-29

申请号：US17898923

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22

CPC classification number: G11C11/2257

Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a word line to precharge the word line. A memory device may include voltage shaping circuitry and a memory controller. The memory controller may cause the voltage shaping circuitry to adjust a characteristic of a word line select control signal transmitted via the word line prior to the word line select control signal being transmitted to a memory cell.

公开(公告)号：US11900980B2

公开(公告)日：2024-02-13

申请号：US17690614

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/12 ,  G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

公开(公告)号：US20230395115A1

公开(公告)日：2023-12-07

申请号：US17831368

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jonathan J. Strand

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.

公开(公告)号：US11749330B2

公开(公告)日：2023-09-05

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US20230229560A1

公开(公告)日：2023-07-20

申请号：US17897037

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G06F11/14 ,  G06F12/06 ,  G06F11/10

CPC classification number: G06F11/1435 ,  G06F12/0646 ,  G06F11/1044 ,  G06F2212/1032 ,  G06F2201/805

Abstract: There are provided methods and systems for correcting an error from a memory. For example, there is provided a system for mitigating an error in a memory. The system can include a memory controller communicatively coupled to a host. The memory controller may be configured to receive information associated with a memory location. The information can indicate the error at the memory location. The controller may be configured to perform, upon receiving the information, certain operations. The operations can include copying data around the memory location, placing the copied data in a reserved area. And the operations can further include outputting, to a central controller, a set of physical addresses associated with the reserved area, wherein the central controller is configured to modify the set of physical address to conduct a data recovery off-line.

公开(公告)号：US11670357B2

公开(公告)日：2023-06-06

申请号：US17350757

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir J. Javanifard

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4072 ,  G11C11/22

CPC classification number: G11C11/4074 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2297 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4096

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.